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Youtao Zhang

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Chen, Z., Zhang, Y., & Xiao, N. (2021). CacheTree: Reducing Integrity Verification Overhead of Secure Nonvolatile Memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(7), 1340-1353.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2020.3015925.

Ding, S., Hu, S., Li, X., Zhang, Y., & Wu, D.D. (2021). Leveraging Multimodal Semantic Fusion for Gastric Cancer Screening via Hierarchical Attention Mechanism. IEEE Transactions on Systems, Man, and Cybernetics: Systems, 1-14.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tsmc.2021.3096974.

Wang, H., Ding, S., Li, Y., Li, X., & Zhang, Y. (2021). Hierarchical Physician Recommendation via Diversity-enhanced Matrix Factorization. ACM TRANSACTIONS ON KNOWLEDGE DISCOVERY FROM DATA, 15(1), 1-17.Association for Computing Machinery (ACM). doi: 10.1145/3418227.

Yue, Z., Ding, S., Li, X., Yang, S., & Zhang, Y. (2021). Automatic Acetowhite Lesion Segmentation via Specular Reflection Removal and Deep Attention Network. IEEE J Biomed Health Inform, 25(9), 3529-3540.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JBHI.2021.3064366.

Yue, Z., Ding, S., Yang, S., Yang, H., Li, Z., Zhang, Y., & Li, Y. (2021). Deep Super-Resolution Network for rPPG Information Recovery and Noncontact Heart Rate Estimation. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 70, 1-11.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TIM.2021.3109398.

Yue, Z., Ding, S., Zhao, L., Zhang, Y., Cao, Z., Tanveer, M., Jolfaei, A., & Zheng, X. (2021). Privacy-preserving Time-series Medical Images Analysis Using a Hybrid Deep Learning Framework. ACM Transactions on Internet Technology, 21(3), 1-21.Association for Computing Machinery (ACM). doi: 10.1145/3383779.

Cui, J., Zhang, Y., Shi, L., Xue, C.J., Yang, J., Liu, W., & Yang, L.T. (2020). Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems. JOURNAL OF SYSTEMS ARCHITECTURE, 103, 101685.Elsevier BV. doi: 10.1016/j.sysarc.2019.101685.

Deng, Q., Zhang, Y., Zhao, Z., Zhang, S., Zhang, M., & Yang, J. (2020). FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2396-2409.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2946808.

Ding, S., Yue, Z., Yang, S., Niu, F., & Zhang, Y. (2020). A Novel Trust Model Based Overlapping Community Detection Algorithm for Social Networks. IEEE Transactions on Knowledge and Data Engineering, 32(11), 2101-2114.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tkde.2019.2914201.

Gao, C., Shi, L., Li, Q., Liu, K., Xue, C.J., Yang, J., & Zhang, Y. (2020). Aging Capacitor Supported Cache Management Scheme for Solid-State Drives. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2230-2239.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2949541.

Gao, C., Shi, L., Liu, K., Xue, C.J., Yang, J., & Zhang, Y. (2020). Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 31(9), 2185-2200.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2020.2987894.

Li, C., Zigerelli, A., Yang, J., Zhang, Y., Ma, S., & Guo, Y. (2020). A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(1), 75-87.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2018.2883906.

Wen, W., Zhao, L., Zhang, Y., & Yang, J. (2020). Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2347-2360.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2940685.

Yue, Z., Ding, S., Zhao, W., Wang, H., Ma, J., Zhang, Y., Zhang, Y. (2020). Automatic CIN Grades Prediction of Sequential Cervigram Image Using LSTM With Multistate CNN Features. IEEE JOURNAL OF BIOMEDICAL AND HEALTH INFORMATICS, 24(3), 844-854.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JBHI.2019.2922682.

Wang, H., Ding, S., Wu, D., Zhang, Y., & Yang, S. (2019). Smart connected electronic gastroscope system for gastric cancer screening using multi-column convolutional neural networks. INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 57(21), 6795-6806.Informa UK Limited. doi: 10.1080/00207543.2018.1464232.

Xie, M., Pan, C., Zhang, Y., Hu, J., Liu, Y., & Xue, C.J. (2019). A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices. IEEE MICRO, 39(1), 24-32.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2018.2890257.

Chen, D., Wang, L., Su, T., & Zhang, Y. (2018). Canonical Correlation Analysis Between Residents' Living Standards and Community Management Service Levels in Rural Areas: An EmpiricalAnalysisBased on Municipal Data in Anhui Province. COMPUTATIONAL ECONOMICS, 52(4), 1053-1068.Springer Science and Business Media LLC. doi: 10.1007/s10614-017-9791-4.

Chen, Y., Ding, S., Zheng, H., Zhang, Y., & Yang, S. (2018). Exploring diffusion strategies for mHealth promotion using evolutionary game model. Applied Mathematics and Computation, 336, 148-161.Elsevier BV. doi: 10.1016/j.amc.2018.04.062.

Cui, J., Zhang, Y., Shi, L., Xue, C.J., Wu, W., & Yang, J. (2018). ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(10), 1957-1970.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2017.2782765.

Cui, J., Zhang, Y., Wu, W., Yang, J., Wang, Y., & Huang, J. (2018). DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(8), 1546-1559.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2017.2766156.

Ding, S., Li, Y., Wu, D., Zhang, Y., & Yang, S. (2018). Time-aware cloud service recommendation using similarity-enhanced collaborative filtering and ARIMA model. Decision Support Systems, 107, 103-115.Elsevier BV. doi: 10.1016/j.dss.2017.12.012.

Ding, S., Xia, C., Wang, C., Wu, D., & Zhang, Y. (2017). Multi-objective optimization based ranking prediction for cloud service recommendation. Decision Support Systems, 101, 106-114.Elsevier BV. doi: 10.1016/j.dss.2017.06.005.

Wen, W., Yang, J., & Zhang, Y. (2017). Optimizing power efficiency for 3D stacked GPU-in-memory architecture. MICROPROCESSORS AND MICROSYSTEMS, 49, 44-53.Elsevier BV. doi: 10.1016/j.micpro.2017.01.005.

Zhang, X., Zhang, Y., Childers, B.R., & Yang, J. (2017). On the Restore Time Variations of Future DRAM Memory. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 22(2), 1-24.Association for Computing Machinery (ACM). doi: 10.1145/2967609.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2016). Simultaneous Multikernel: Fine-Grained Sharing of GPUs. IEEE COMPUTER ARCHITECTURE LETTERS, 15(2), 113-116.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2015.2477405.

Jiang, L., Zhao, B., Yang, J., & Zhang, Y. (2015). Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 20(4), 1-24.Association for Computing Machinery (ACM). doi: 10.1145/2764903.

Wang, R., Jiang, L., Zhang, Y., & Yang, J. (2015). SD-PCM Constructing Reliable Super Dense Phase Change Memory under Write Disturbance. ACM SIGPLAN NOTICES, 50(4), 19-31.ACM. doi: 10.1145/2694344.2694352.

Xu, Y., Zhao, B., Zhang, Y., & Yang, J. (2015). Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers. ACM Transactions on Parallel Computing, 2(1), 1-23.Association for Computing Machinery (ACM). doi: 10.1145/2742349.

Zhao, M., Jiang, L., Shi, L., Zhang, Y., & Xue, C.J. (2015). Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 34(2), 227-237.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2014.2376989.

Ding, S., Yang, S., Zhang, Y., Liang, C., & Xia, C. (2014). Combining QoS prediction and customer satisfaction estimation to solve cloud service trustworthiness evaluation problems. Knowledge-Based Systems, 56, 216-225.Elsevier BV. doi: 10.1016/j.knosys.2013.11.014.

Zhang, Y., & Kulkarni, P. (2014). Foreword. ACM SIGPLAN Notices, 49(5), iii.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2014). Erratum: Process variation-aware nonuniform cache management in a 3d die-stacked multicore processor (IEEE Transactions on Computers (2013) 62:11 (2252-2265)). IEEE Transactions on Computers, 63(2), 525-526. doi: 10.1109/TC.2014.5.

Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2014). Throughput Enhancement for Phase Change Memories. IEEE TRANSACTIONS ON COMPUTERS, 63(8), 2080-2093.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2013.76.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B.R., & Yang, J. (2013). Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(2), 1-25.Association for Computing Machinery (ACM). doi: 10.1145/2459316.2459318.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B.R., & Yang, J. (2013). Hardware-assisted cooperative integration of wear-leveling and salvaging for phase change memory. Transactions on Architecture and Code Optimization, 10(2). doi: 10.1145/2459316.2459.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2013). Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor. IEEE TRANSACTIONS ON COMPUTERS, 62(11), 2252-2265.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2012.129.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2013). Common-Source-Line Array: An Area Efficient Memory Architecture for Bipolar Nonvolatile Devices. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 18(4), 1-18.Association for Computing Machinery (ACM). doi: 10.1145/2500459.

Lee, B.C., Zhou, P., Yang, J., Zhang, Y., Zhao, B., Ipek, E., Mutlu, O., & Burger, D. (2010). PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY. IEEE MICRO, 30(1), 131-141.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2010.24.

Li, W., & Zhang, Y. (2010). An efficient code update scheme for DSP applications in mobile embedded systems. ACM SIGPLAN Notices, 45(4), 105-114.Association for Computing Machinery (ACM). doi: 10.1145/1755951.1755904.

Yang, J., Gao, L., Zhang, Y., Chrobak, M., & Lee, H.H.S. (2010). A low-cost memory remapping scheme for address bus protection. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 70(5), 443-457.Elsevier BV. doi: 10.1016/j.jpdc.2009.11.008.

Zhang, Y., Yang, J., Li, W., Wang, L., & Jin, L. (2010). An authentication scheme for locating compromised sensor nodes in WSNs. JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, 33(1), 50-62.Elsevier BV. doi: 10.1016/j.jnca.2009.06.003.

Zhang, Y., Yang, J., Vu, H.T., & Wu, Y. (2010). The design and evaluation of interleaved authentication for filtering false reports in multipath routing WSNs. WIRELESS NETWORKS, 16(1), 125-140.Springer Science and Business Media LLC. doi: 10.1007/s11276-008-0119-0.

Zhou, X., Yang, J., Chrobak, M., & Zhang, Y. (2010). Performance-Aware Thermal Management via Task Scheduling. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(1). doi: 10.1145/1746065.1736070.

Zhou, X., Yang, J., Chrobak, M., & Zhang, Y. (2010). Performance-aware thermal management via task scheduling. ACM Transactions on Architecture and Code Optimization, 7(1), 1-31.Association for Computing Machinery (ACM). doi: 10.1145/1736065.1736070.

Zhou, X., Yang, J., Xu, Y., Zhang, Y., & Zhao, J. (2010). Thermal-Aware Task Scheduling for 3D Multicore Processors. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 21(1), 60-71.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2009.27.

Allen, U., Humar, A., Limaye, A., Michaels, M., & Miller, R. (2009). Discipline of Transplant Infectious Diseases (ID). Foreword. Am J Transplant, 9 Suppl 4, S1-S2.Wiley. doi: 10.1111/j.1600-6143.2009.02886.x.

Li, W., Zhang, Y., Yang, J., & Zheng, J. (2009). Towards Update-Conscious Compilation for Energy-Efficient Code Dissemination in WSNs. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(4), 1-33.Association for Computing Machinery (ACM). doi: 10.1145/1596510.1596512.

Zhang, Y., Yang, J., & Gao, L. (2009). Supporting flexible streaming media protection through privacy-aware secure processors. COMPUTERS & ELECTRICAL ENGINEERING, 35(2), 286-299.Elsevier BV. doi: 10.1016/j.compeleceng.2008.06.001.

Lin, Y., Zhang, Y., & Gupta, R. (2007). The design and evaluation of path matching schemes on compressed control flow traces. Journal of Systems and Software, 80(3), 396-409.Elsevier BV. doi: 10.1016/j.jss.2006.06.007.

Zhang, Y., & Gupta, R. (2006). Compressing heap data for improved memory performance. Software: Practice and Experience, 36(10), 1081-1111.Wiley. doi: 10.1002/spe.729.

Yang, J., Gao, L., & Zhang, Y.T. (2005). Improving memory encryption performance in secure processors. IEEE TRANSACTIONS ON COMPUTERS, 54(5), 630-640.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2005.80.

Yang, J., Yu, J., & Zhang, Y.T. (2005). A low energy cache design for multimedia applications exploiting set access locality. JOURNAL OF SYSTEMS ARCHITECTURE, 51(10-11), 653-664.Elsevier BV. doi: 10.1016/j.sysarc.2005.02.003.

Zhang, X., Gupta, R., & Zhang, Y. (2005). Cost and precision tradeoffs of dynamic data slicing algorithms. ACM Transactions on Programming Languages and Systems, 27(4), 631-661.Association for Computing Machinery (ACM). doi: 10.1145/1075382.1075384.

Gupta, R., Mehofer, E., & Zhang, Y. (2002). The Compiler Design Handbook. In The Compiler Design Handbook: Optimizations and Machine Code Generation. (pp. 143-174).CRC Press. doi: 10.1201/9781420040579.

Zhang, Y., & Gupta, R. (2001). Timestamped whole program path representation and its applications. ACM SIGPLAN Notices, 36(5), 180-190.Association for Computing Machinery (ACM). doi: 10.1145/381694.378835.

Zhang, Y., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. ACM SIGOPS Operating Systems Review, 34(5), 150-159.Association for Computing Machinery (ACM). doi: 10.1145/384264.379235.

Zhang, Y., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. ACM SIGPLAN Notices, 35(11), 150-159.Association for Computing Machinery (ACM). doi: 10.1145/356989.357003.

Guo, Y., Zigerelli, A., Zhang, Y., & Yang, J. (2021). IVcache. In Proceedings of the 2021 on Great Lakes Symposium on VLSI, (pp. 403-408).ACM. doi: 10.1145/3453688.3461481.

Xu, W., Zhang, Y., & Tang, X. (2021). Parallelizing DNN Training on GPUs: Challenges and Opportunities. In Companion Proceedings of the Web Conference 2021, (pp. 174-178).ACM. doi: 10.1145/3442442.3452055.

Nie, S., Zhang, Y., Wu, W., & Yang, J. (2020). Layer RBER Variation Aware Read Performance Optimization for 3D Flash Memories. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020-July.IEEE. doi: 10.1109/dac18072.2020.9218631.

Wen, W., Zhang, Y., & Yang, J. (2020). Accelerating 3D vertical resistive memories with opportunistic write latency reduction. In Proceedings of the 39th International Conference on Computer-Aided Design, 2020-November.ACM. doi: 10.1145/3400302.3415677.

Xin, X., Zhang, Y., & Yang, J. (2020). ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 303-314).IEEE. doi: 10.1109/hpca47549.2020.00033.

Xin, X., Zhang, Y., & Yang, J. (2020). Reducing DRAM Access Latency via Helper Rows. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020-July.IEEE. doi: 10.1109/dac18072.2020.9218719.

Zhao, L., Zhang, Y., & Yang, J. (2020). SCA: A Secure CNN Accelerator for Both Training and Inference. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020-July.IEEE. doi: 10.1109/dac18072.2020.9218752.

Chen, Z., Deng, Q., Xiao, N., Pruhs, K., & Zhang, Y. (2019). DWMAcc. In ACM Transactions on Embedded Computing Systems, 18(5s), (pp. 1-19).Association for Computing Machinery (ACM). doi: 10.1145/3358199.

Deng, Q., Zhang, Y., Zhang, M., & Yang, J. (2019). LAcc. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317845.

Gao, C., Shi, L., Xue, C.J., Ji, C., Yang, J., & Zhang, Y. (2019). Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs. In 2019 35th Symposium on Mass Storage Systems and Technologies (MSST), 2019-May, (pp. 172-184).IEEE. doi: 10.1109/msst.2019.000-5.

Gao, C., Ye, M., Li, Q., Xue, C.J., Zhang, Y., Shi, L., & Yang, J. (2019). Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 493-505).ACM. doi: 10.1145/3352460.3358323.

Li, C., Ausavarungnirun, R., Rossbach, C.J., Zhang, Y., Mutlu, O., Guo, Y., & Yang, J. (2019). A Framework for Memory Oversubscription Management in Graphics Processing Units. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, (pp. 49-63).ACM. doi: 10.1145/3297858.3304044.

Li, Q., Shi, L., Yang, J., Zhang, Y., & Xue, C.J. (2019). Leveraging Approximate Data for Robust Flash Storage. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317848.

Liu, L., Wang, R., Zhang, Y., & Yang, J. (2019). H-ORAM. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317841.

Nie, S., Zhang, Y., Wu, W., Zhang, C., & Yang, J. (2019). DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs. In 2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA).IEEE. doi: 10.1109/nvmsa.2019.8863520.

Raoufi, M., Deng, Q., Zhang, Y., & Yang, J. (2019). PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019-July, (pp. 82-87).IEEE. doi: 10.1109/isvlsi.2019.00023.

Wen, W., Zhang, Y., & Yang, J. (2019). ReNEW: Enhancing Lifetime for ReRAM Crossbar Based Neural Network Accelerators. In 2019 IEEE 37th International Conference on Computer Design (ICCD), (pp. 487-496).IEEE. doi: 10.1109/iccd46524.2019.00074.

Xin, X., Zhang, Y., & Yang, J. (2019). ROC. In Proceedings of the 56th Annual Design Automation Conference 2019.ACM. doi: 10.1145/3316781.3317900.

Zhang, X., Wang, R., Zhang, Y., & Yang, J. (2019). Boosting chipkill capability under retention-error induced reliability emergency. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, (pp. 438-443).ACM. doi: 10.1145/3287624.3287639.

Zhao, L., Deng, Q., Zhang, Y., & Yang, J. (2019). RFAcc. In Proceedings of the ACM International Conference on Supercomputing, (pp. 473-483).ACM. doi: 10.1145/3330345.3330387.

Cui, J., Zhang, Y., Huang, J., Wu, W., & Yang, J. (2018). ShadowGC: Cooperative garbage collection with multi-level buffer for performance improvement in NAND flash-based SSDs. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-January, (pp. 1247-1252).IEEE. doi: 10.23919/date.2018.8342206.

Deng, Q., Jiang, L., Zhang, Y., Zhang, M., & Yang, J. (2018). DrAcc. In Proceedings of the 55th Annual Design Automation Conference, Part F137710.ACM. doi: 10.1145/3195970.3196029.

Garrett, T., Yang, J., & Zhang, Y. (2018). Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection. In Proceedings of the International Symposium on Low Power Electronics and Design.ACM. doi: 10.1145/3218603.3218627.

Wang, R., Zhang, Y., & Yang, J. (2018). D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018-February, (pp. 416-427).IEEE. doi: 10.1109/hpca.2018.00043.

Wen, W., Zhang, Y., & Yang, J. (2018). Wear leveling for crossbar resistive memory. In Proceedings of the 55th Annual Design Automation Conference, Part F137710.ACM. doi: 10.1145/3195970.3196138.

Deng, Q., Zhang, Y., Zhang, M., & Yang, J. (2017). Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 736-742).IEEE. doi: 10.1109/iccad.2017.8203850.

Lei Zhao, Lei Jiang, Youtao Zhang, Nong Xiao, & Jun Yang. (2017). Constructing fast and energy efficient 1TnR based ReRAM crossbar memory. In 2017 18th International Symposium on Quality Electronic Design (ISQED), (pp. 58-64).IEEE. doi: 10.1109/isqed.2017.7918293.

Wang, R., Zhang, Y., & Yang, J. (2017). Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 325-336).IEEE. doi: 10.1109/hpca.2017.9.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2017). Quality of Service Support for Fine-Grained Sharing on GPUs. In Proceedings of the 44th Annual International Symposium on Computer Architecture, Part F128643, (pp. 269-281).ACM. doi: 10.1145/3079856.3080203.

Wen, W., Zhang, Y., & Yang, J. (2017). Read Error Resilient MLC STT-MRAM Based Last Level Cache. In 2017 IEEE International Conference on Computer Design (ICCD), (pp. 455-462).IEEE. doi: 10.1109/iccd.2017.80.

Wen, W., Zhao, L., Zhang, Y., & Yang, J. (2017). Speeding up crossbar resistive memory by exploiting in-memory data patterns. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 261-267).IEEE. doi: 10.1109/iccad.2017.8203787.

Zhang, X., Zhang, Y., Childers, B.R., & Yang, J. (2017). DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing. In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2017-September, (pp. 53-63).IEEE. doi: 10.1109/pact.2017.34.

Zhao, L., Zhang, Y., & Yang, J. (2017). Mitigating shift-based covert-channel attacks in racetrack last level caches. In 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA).IEEE. doi: 10.1109/nvmsa.2017.8064476.

Zhao, L., Zhang, Y., & Yang, J. (2017). AEP: An error-bearing neural network accelerator for energy efficiency and model protection. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 1047-1053).IEEE. doi: 10.1109/iccad.2017.8203897.

Zhao, L., Zhang, Y., & Yang, J. (2017). AEP: An error-bearing neural network accelerator for energy efficiency and model protection. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 765-771).IEEE. doi: 10.1109/iccad.2017.8203854.

Wang, R., Zhang, Y., & Yang, J. (2016). ReadDuo: Constructing Reliable MLC Phase Change Memory through Fast and Robust Readout. In 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), (pp. 203-214).IEEE. doi: 10.1109/dsn.2016.27.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2016). Simultaneous Multikernel GPU: Multi-tasking throughput processors via fine-grained sharing. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016-April, (pp. 358-369).IEEE. doi: 10.1109/hpca.2016.7446078.

Wu, Y., Zhu, M., Li, D., Zhang, Y., & Wang, Y. (2016). Brain stroke localization by using microwave-based signal classification. In 2016 International Conference on Electromagnetics in Advanced Applications (ICEAA), (pp. 828-831).IEEE. doi: 10.1109/iceaa.2016.7731527.

Xie, M., Zhao, M., Pan, C., Li, H., Liu, Y., Zhang, Y., Xue, C.J., & Hu, J. (2016). Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems. In Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis.ACM. doi: 10.1145/2968456.2968477.

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