(2012) Graphene research covered in Nature article on graphene electronics.
(2011) Top accessed article, IEEE Trans. Computer-aided Design.
(2011) Top accessed article, IEEE Trans. Nanotechnology.
(2011) Top accessed article, IEEE Electron Device Letters.
(2011) Finalist, Phi Beta Kappa Teaching Prize, Rice University.
(2010) Best paper award nomination, International Conference on Computer-aided Design.
(2010) Distinguished Faculty Associate, McMurtry College, Rice University.
(2010) Finalist, Phi Beta Kappa Teaching Prize, Rice University.
(2010) ACS Nano article covered by MIT Technology Review, Physics World, Nanowerk, EE Times, and other technology portals.
(2009) Top 10 downloaded papers, IEEE Transactions on Computer-aided Design.
(2009 - 2011) Associate Editor, IEEE Transactions on VLSI Systems.
(2008) National Science Foundation CAREER Award.
(2007) A. Richard Newton Graduate Scholarship.
(2006) Technical Leadership Award, ACM Special Interest Group on Design Automation (ACM/SIGDA).
PhD, Computer Engineering. Thesis: "Reliability and test of high-speed integrated circuits", University of Texas, 2003
MS, Computer Engineering. Thesis: "Recent advances in partitioned ordered binary decision diagrams", University of Texas, 2000
BTech, Electrical Engineering, Indian Institute of Technology, 1998
Rakshit, J., & Mohanram, K. (2018). LEO: Low Overhead Encryption ORAM for Non-Volatile Memories. IEEE COMPUTER ARCHITECTURE LETTERS, 17(2), 100-104.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2018.2795621.
Swami, S., & Mohanram, K. (2018). ARSENAL: Architecture for Secure Non-Volatile Memories. IEEE COMPUTER ARCHITECTURE LETTERS, 17(2), 192-196.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2018.2863281.
Palangappa, P.M., & Mohanram, K. (2017). CompEx plus plus : Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 14(1), 1-30.Association for Computing Machinery (ACM). doi: 10.1145/3050440.
Rakshit, J., Mohanram, K., Wan, R., Lam, K.T., & Guo, J. (2017). Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 13(2), 1-28.Association for Computing Machinery (ACM). doi: 10.1145/2967613.
Swami, S., & Mohanram, K. (2017). Reliable Nonvolatile Memories: Techniques and Measures. IEEE DESIGN & TEST, 34(3), 31-41.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MDAT.2017.2682252.
Swami, S., Palangappa, P.M., & Mohanram, K. (2017). ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memoriese. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 14(4), 1-29.Association for Computing Machinery (ACM). doi: 10.1145/3151083.
Mohanram, K., & Mirnalinee, T.T. (2016). Intelligent techniques for location based services using medical information retrieval in cloud database. Asian Journal of Information Technology, 15(14), 2367-2370. doi: 10.3923/ajit.2016.2367.2370.
Palangappa, P.M., Li, J., & Mohanram, K. (2016). WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory. IEEE TRANSACTIONS ON COMPUTERS, 65(4), 1025-1040.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2015.2506555.
Li, J., Dgien, D.B., Hunter, N.A., Zhao, Y., & Mohanram, K. (2015). Two-Port PCM Architecture for Network Processing. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23(10), 2135-2148.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2014.2360801.
Choudhury, M.R., Chandra, V., Aitken, R.C., & Mohanram, K. (2014). Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE TRANSACTIONS ON COMPUTERS, 63(2), 497-509.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2012.190.
Choudhury, M.R., & Mohanram, K. (2013). Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 32(8), 1163-1176.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2013.2250581.
Garg, A., Mohanram, K., Di Cara, A., Degueurce, G., Ibberson, M., Dorier, J., & Xenarios, I. (2013). Efficient computation of minimal perturbation sets in gene regulatory networks. Front Physiol, 4, 361.Frontiers. doi: 10.3389/fphys.2013.00361.
Garg, A., Mohanram, K., De Micheli, G., & Xenarios, I. (2012). Implicit methods for qualitative modeling of gene regulatory networks. In Gene Regulatory Networks. 786, (pp. 397-443).Springer Nature. doi: 10.1007/978-1-61779-292-2_22.
Ben-Jamaa, M.H., Mohanram, K., & De Micheli, G. (2011). An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 30(2), 242-255.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2010.2085250.
Choudhury, M.R., Yoon, Y., Guo, J., & Mohanram, K. (2011). Graphene Nanoribbon FETs: Technology Exploration for Performance and Reliability. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 10(4), 727-736.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TNANO.2010.2073718.
Mohanram, K., & Yang, X. (2011). Graphene Transistors and Circuits. In Nanoelectronic Circuit Design. (pp. 349-376).Springer Nature. doi: 10.1007/978-1-4419-7609-3_10.
Rostami, M., & Mohanram, K. (2011). Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 30(3), 337-349.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2010.2097310.
Yang, X., & Mohanram, K. (2011). Modeling and Performance Investigation of the Double-Gate Carbon Nanotube Transistor. IEEE ELECTRON DEVICE LETTERS, 32(3), 231-233.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LED.2010.2095826.
Yang, X., Liu, G., Rostami, M., Balandin, A.A., & Mohanram, K. (2011). Graphene Ambipolar Multiplier Phase Detector. IEEE ELECTRON DEVICE LETTERS, 32(10), 1328-1330.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LED.2011.2162576.
Yang, X., Liu, G., Balandin, A.A., & Mohanram, K. (2010). Triple-mode single-transistor graphene amplifier and its applications. ACS Nano, 4(10), 5532-5538.American Chemical Society (ACS). doi: 10.1021/nn1021583.
Choudhury, M., Zhou, Q., & Mohanram, K. (2009). Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 25(2-3), 197-207.Springer Nature. doi: 10.1007/s10836-009-5103-9.
Choudhury, M.R., & Mohanram, K. (2009). Reliability Analysis of Logic Circuits. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 28(3), 392-405.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2009.2012530.
Choudhury, M.R., & Mohanram, K. (2009). Reliability Analysis of Logic Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(3), 392-405.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tcad.2009.2012530.
Garg, A., Mohanram, K., Di Cara, A., De Micheli, G., & Xenarios, I. (2009). Modeling stochasticity and robustness in gene regulatory networks. Bioinformatics, 25(12), i101-i109.Oxford University Press (OUP). doi: 10.1093/bioinformatics/btp214.
Massoud, Y., Kirolos, S., & Mohanram, K. (2009). Analytical model-based technique for efficient evaluation of noise robustness considering parameter variations. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 60(1-2), 27-34.Springer Nature. doi: 10.1007/s10470-008-9200-y.
Zhao, P., Choudhury, M., Mohanram, K., & Guo, J. (2008). Computational Model of Edge Effects in Graphene Nanoribbon Transistors. NANO RESEARCH, 1(5), 395-402.Tsinghua University Press. doi: 10.1007/s12274-008-8039-y.
Zhou, Q.M., & Mohanram, K. (2006). Gate sizing to radiation harden combinational logic. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(1), 155-166.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2005.853696.
Mohanram, K., & Touba, N.A. (2004). Lowering power consumption in concurrent checkers via input ordering. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 12(11), 1234-1243.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2004.836318.
Avinash, P., Professor, K.M., Rajasekhar, K., & Naik, D. (2019). Protected and Flexible Multi-Keyword Score Search model over Encoded Cloud Data. In Journal of Physics Conference Series, 1228(1), (p. 012058).IOP Publishing. doi: 10.1088/1742-6596/1228/1/012058.
Alsuwaiyan, A., & Mohanram, K. (2018). MFNW: An MLC/TLC Flip-N-Write Architecture. In ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 14(2), (pp. 1-32).Association for Computing Machinery (ACM). doi: 10.1145/3154841.
Palangappa, P.M., & Mohanram, K. (2018). CASTLE. In Proceedings of the 55th Annual Design Automation Conference, Part F137710, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3195970.3196007.
Palangappa, P.M., & Mohanram, K. (2018). RAPID. In Proceedings of the International Conference on Computer-Aided Design, (pp. 1-7).Association for Computing Machinery (ACM). doi: 10.1145/3240765.3240840.
Rakshit, J., & Mohanram, K. (2018). ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories. In 2018 IEEE 36th International Conference on Computer Design (ICCD), (pp. 100-107).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2018.00024.
Swami, S., & Mohanram, K. (2018). ADAM: Architecture for Write Disturbance Mitigation in Scaled Phase Change Memory. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-January, (pp. 1235-1240).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.23919/date.2018.8342204.
Swami, S., & Mohanram, K. (2018). ACME. In Proceedings of the 55th Annual Design Automation Conference, Part F137710, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3195970.3195983.
Swami, S., Rakshit, J., & Mohanram, K. (2018). STASH. In Proceedings of the 55th Annual Design Automation Conference, Part F137710, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3195970.3196123.
Alsuwaiyan, A., & Mohanram, K. (2017). L3EP: Low Latency, Low Energy Program-and-Verify for Triple-Level Cell Phase Change Memory. In 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), (pp. 27-32).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nanoarch.2017.8053710.
Li, J., & Mohanram, K. (2017). Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies. In 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), (pp. 47-52).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/vlsid.2017.13.
Mohanram, K., & Mirnalinee, T. (2017). Secured Data Storage and Retrieval Techniques for Effective Handling of Transport Data. In 2017 Second International Conference on Recent Trends and Challenges in Computational Models (ICRTCCM), (pp. 239-243).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icrtccm.2017.76.
Rakshit, J., & Mohanram, K. (2017). ASSURE. In Proceedings of the 54th Annual Design Automation Conference 2017, Part 128280, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3061639.3062205.
Swami, S., & Mohanram, K. (2017). Covert: Counter Overflow ReducTion for Efficient Encryption of Non-Volatile Memories. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, (pp. 906-909).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.23919/date.2017.7927117.
Alsuwaiyan, A., & Mohanram, K. (2016). An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories. In Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 18-20-May-2016, (pp. 403-408).Association for Computing Machinery (ACM). doi: 10.1145/2902961.2902979.
Palangappa, P.M., & Mohanram, K. (2016). CompEx: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVM. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016-April, (pp. 90-101).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2016.7446056.
Swami, S., & Mohanram, K. (2016). E3 R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-Volatile Memories. In 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016-March, (pp. 373-378).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/vlsid.2016.33.
Swami, S., Rakshit, J., & Mohanram, K. (2016). SECRET. In Proceedings of the 53rd Annual Design Automation Conference, 05-09-June-2016, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/2897937.2898087.
Alsuwaiyan, A., & Mohanram, K. (2015). MFNW: A Flip-N-Write Architecture for Multi-Level Cell Non-Volatile Memories. In Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15), (pp. 13-18).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nanoarch.2015.7180577.
Palangappa, P.M., & Mohanram, K. (2015). Flip-Mirror-Rotate. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 20-22-May-2015, (pp. 221-224).Association for Computing Machinery (ACM). doi: 10.1145/2742060.2742110.
Rakshit, J., Wan, R., Lam, K.T., Guo, J., & Mohanram, K. (2015). Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/2744769.2744872.
Dgien, D.B., Palangappa, P.M., Hunter, N.A., Li, J., & Mohanram, K. (2014). Compression Architecture for Bit-write Reduction in Non-volatile Memory Technologies. In 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), (pp. 51-56).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nanoarch.2014.6880482.
Li, J., & Mohanram, K. (2014). Write-Once-Memory-Code Phase Change Memory. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, (pp. 1-6).EDAA. doi: 10.7873/date2014.194.
Mohanram, K., Wartell, M., & iyer, S. (2013). Mempack: An Order of Magnitude Reduction in the Cost, Risk, and Time for Memory Compiler Certification. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (pp. 1490-1493).EDAA. doi: 10.7873/date.2013.303.
Zhao, Y., Li, J., & Mohanram, K. (2013). Multi-port FinFET SRAM design. In Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, (pp. 293-298).Association for Computing Machinery (ACM). doi: 10.1145/2483028.2483113.
Du, K., Varman, P., & Mohanram, K. (2012). High performance reliable variable latency carry select addition. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1257-1262).
Mohanram, K., Yang, X., Rostami, M., Liu, G., & Balandin, A. (2012). Ambipolar circuits for analog, mixed-signal, and radio-frequency applications. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/2765491.2765493.
Du, K., Varman, P., & Mohanram, K. (2011). Static Window Addition: A New Paradigm for the Design of Variable Latency Adders. In 2011 IEEE 29th International Conference on Computer Design (ICCD), (pp. 455-456).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2011.6081446.
Yang, X., & Mohanram, K. (2011). Unequal-error-protection codes in SRAMs for mobile multimedia applications. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 21-27).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2011.6105300.
Yang, X., & Mohanram, K. (2011). Robust 6T Si tunneling transistor SRAM design. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 740-745).
Zukoski, A., Choudhury, M.R., & Mohanram, K. (2011). Reliability-driven don't care assignment for logic synthesis. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1560-1565).
Zukoski, A., Yang, X., & Mohanram, K. (2011). Universal logic modules based on double-gate carbon nanotube transistors. In Proceedings of the 48th Design Automation Conference, (pp. 884-889).Association for Computing Machinery (ACM). doi: 10.1145/2024724.2024921.
Choudhury, M., & Mohanram, K. (2010). Bi-decomposition of large Boolean functions using blocking edge graphs. In 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 586-591).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2010.5654210.
Choudhury, M., Chandhury, V., Mohanram, K., & Aitken, R. (2010). Analytical Model for TDDB-Based Performance Degradation in Combinational Logic. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), (pp. 423-428).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2010.5457168.
Choudhury, M., Chandra, V., Mohanram, K., & Aitken, R. (2010). TIMBER: Time Borrowing and Error Relaying for Online Timing Error Resilience. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), (pp. 1554-1559).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2010.5457058.
Choudhury, M., Rostami, M., & Mohanram, K. (2010). Dominant critical gate identification for power and yield optimization in logic circuits. In Proceedings of the 20th symposium on Great lakes symposium on VLSI, (pp. 173-178).Association for Computing Machinery (ACM). doi: 10.1145/1785481.1785526.
Jamaa, M.H.B., Mohanram, K., & De Micheli, G. (2010). Power consumption of logic circuits in ambipolar carbon nanotube technology. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 303-306).
Rostami, M., & Mohanram, K. (2010). Novel dual-Vth independent-gate FinFET circuits. In 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 867-872).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/aspdac.2010.5419680.
Yang, X., Chauhan, J., Guo, J., & Mohanram, K. (2010). Graphene tunneling FET and its applications in low-power circuit design. In Proceedings of the 20th symposium on Great lakes symposium on VLSI, (pp. 263-268).Association for Computing Machinery (ACM). doi: 10.1145/1785481.1785544.
Yang, X., Fiori, G., Iannaccone, G., & Mohanram, K. (2010). Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. In Proceedings of the 20th symposium on Great lakes symposium on VLSI, (pp. 233-238).Association for Computing Machinery (ACM). doi: 10.1145/1785481.1785538.
Choudhury, M., & Mohanram, K. (2009). Timing-driven optimization using lookahead logic circuits. In Proceedings of the 46th Annual Design Automation Conference, (pp. 390-395).Association for Computing Machinery (ACM). doi: 10.1145/1629911.1630015.
Choudhury, M.R., & Mohanram, K. (2009). Masking timing errors on speed-paths in logic circuits. In 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), (pp. 87-92).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2009.5090638.
Jamaa, M.H.B., Mohanram, K., & De Micheli, G. (2009). Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 622-627).
Choudhury, M., Yoon, Y., Guo, J., & Mohanram, K. (2008). Technology exploration for graphene nanoribbon FETs. In Proceedings - Design Automation Conference, (pp. 272-277). doi: 10.1109/DAC.2008.4555822.
Choudhury, M.R., & Mohanram, K. (2008). Approximate logic circuits for low overhead, non-intrusive concurrent error detection. In 2008 Design, Automation and Test in Europe, (pp. 903-908).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2008.4484789.
Mohanram, K., & Guo, J. (2008). Graphene nanoribbon FETs: Technology exploration and CAD. In 2008 IEEE/ACM International Conference on Computer-Aided Design, (pp. 412-415).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2008.4681607.
Zhao, P., Choudhury, M., Mohanram, K., & Jing, G. (2008). Analytical Theory of Graphene Nanoribbon Transistors. In 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, (pp. 3-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ndcs.2008.22.
Zhou, Q., Choudhury, M.R., & Mohanram, K. (2008). Tunable transient filters for soft error rate reduction in combinational circuits. In 2008 13th European Test Symposium, (pp. 179-184).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ets.2008.39.
Choudhury, M., Ringgenberg, K., Rixner, S., & Mohanram, K. (2007). Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory. In 2007 Design, Automation & Test in Europe Conference & Exhibition, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2007.364436.
Choudhury, M.R., & Mohanram, K. (2007). Accurate and scalable reliability analysis of logic circuits. In 2007 Design, Automation & Test in Europe Conference & Exhibition, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2007.364503.
Kirolos, S., Mondal, M., Mohanram, K., & Massoud, Y. (2007). Expression of Concern: A model-based technique for efficient evaluation of noise robustness. In 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), (pp. 714-717).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mwscas.2007.4488678.
Mondal, M., Mohanram, K., & Massoud, Y. (2007). Expression of Concern: Parameter-Variation-Aware Analysis for Noise Robustness. In 9th International Symposium on Quality Electronic Design (isqed 2008), (pp. 655-659).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isqed.2007.115.
Sun, K., Zhou, Q., Mohanram, K., & Sorensen, D.C. (2007). Parallel Domain Decomposition for Simulation of Large-Scale Power Grids. In Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design - ICCAD '06, (pp. 54-59).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2007.4397243.
Zhou, Q., Zhong, L., & Mohanram, K. (2007). Power signal processing. In Proceedings of the 2007 international symposium on Low power electronics and design, (pp. 165-170).Association for Computing Machinery (ACM). doi: 10.1145/1283780.1283816.
Choudhury, M.R., Zhou, Q., & Mohanram, K. (2006). Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. In Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design - ICCAD '06, (pp. 204-209).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2006.320137.
Cox, A.L., Mohanram, K., & Rixner, S. (2006). Dependable ≠ unaffordable. In Proceedings of the 1st workshop on Architectural and system support for improving software dependability, (pp. 58-62).Association for Computing Machinery (ACM). doi: 10.1145/1181309.1181318.
Zhou, Q., & Mohanram, K. (2006). Elmore model for energy estimation in RC trees. In Proceedings of the 43rd annual conference on Design automation - DAC '06, (pp. 965-970).Association for Computing Machinery (ACM). doi: 10.1145/1146909.1147154.
Zhou, Q., Choudhury, M.R., & Mohanram, K. (2006). Design optimization for robustness to single-event upsets. In 24th IEEE VLSI Test Symposium, 2006, (pp. 202-207).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/vts.2006.28.
Zhou, Q., Sun, K., Mohanram, K., & Sorensen, D.C. (2006). Large power grid analysis using domain decomposition. In Proceedings -Design, Automation and Test in Europe, DATE, 1, (pp. 27-32).
Mohanram, K. (2005). Simulation of Transients Caused by Single-Event Upsets in Combinational Logic. In IEEE International Conference on Test, 2005., 2005, (pp. 1-9).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/test.2005.1584063.
Mohanram, K. (2005). Closed-form simulation and robustness models for SEU-tolerant design. In 23rd IEEE VLSI Test Symposium (VTS'05), (pp. 327-333).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/vts.2005.35.
Mohanram, K., & Rixner, S. (2005). Context-independent codes for off-chip interconnects. In POWER-AWARE COMPUTER SYSTEMS, 3471, (pp. 107-119).Springer Nature. doi: 10.1007/11574859_8.
Zhou, Q., Mohanram, K., & Antoulas, A.C. (2005). Structure preserving reduction of frequency-dependent interconnect. In Proceedings of the 42nd annual conference on Design automation - DAC '05, (pp. 939-942).Association for Computing Machinery (ACM). doi: 10.1145/1065579.1065824.
Zhou, O., & Mohanram, K. (2004). Analysis of delay caused by bridging faults in RLC interconnects. In Proceedings - International Test Conference, (pp. 1044-1052).
Zhou, Q., & Mohanram, K. (2004). Transistor Sizing for Radiation Hardening. In 2004 IEEE International Reliability Physics Symposium. Proceedings, 2004-January(January), (pp. 310-315).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/relphy.2004.1315343.
Zhou, Q., & Mohanram, K. (2004). Cost-effective radiation hardening technique for combinational logic. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, (pp. 100-106).
Zhou, Q., & Mohanram, K. (2004). Transistor sizing for radiation hardening. In Annual Proceedings - Reliability Physics (Symposium), (pp. 310-315).
Mohanram, K., & Touba, N.A. (2003). Partial error masking to reduce soft error failure rate in logic circuits. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003-January, (pp. 433-440). doi: 10.1109/TSM.2005.1250141.
Mohanram, K., & Touba, N.A. (2003). Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. In IEEE International Test Conference (TC), (pp. 893-901).
Mohanram, K., & Touba, N.A. (2003). Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. In Proceedings. 21st VLSI Test Symposium, 2003., 2003-January, (pp. 121-127).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/vtest.2003.1197642.
Mohanram, K., Sogomonyan, E.S., Gössel, M., & Touba, N.A. (2003). Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. In 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., (pp. 35-40).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/olt.2003.1214364.
Mohanram, K., & Touba, N.A. (2002). Input Ordering in Concurrent Checkers to Reduce Power Consumption. In 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings., 2002-January, (pp. 87-95).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dftvs.2002.1173505.
Mohanram, K., Krishna, C.V., & Touba, N.A. (2002). A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. In Proceedings - IEEE International Symposium on Circuits and Systems, 1, (pp. 577-580).
Jain, J., Mohanram, K., Moundanos, D., Wegener, I., & Lu, Y. (2000). Analysis of composition complexity and how to obtain smaller canonical graphs. In Proceedings-Design Automation Conference, (pp. 681-686). doi: 10.1109/DAC.2000.855401.
Jas, A., Mohanram, K., & Touba, N.A. (1999). Embedded core DFT scheme to obtain highly compressed test sets. In Proceedings of the Asian Test Symposium, (pp. 275-280).