Jun Yang

Ph.D., Computer Science, University of Arizona, 2002

M.S., Computer Science, University of Pittsburgh, 1999

M.A., Applied Mathematics, Worcester Polytechnic Institute, 1997

B.S., Computer Science, Nanjing University, 1995

Cui, J., Zhang, Y., Shi, L., Xue, C.J., Yang, J., Liu, W., & Yang, L.T. (2020). Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems. JOURNAL OF SYSTEMS ARCHITECTURE, 103, 101685.Elsevier. doi: 10.1016/j.sysarc.2019.101685.

Deng, Q., Zhang, Y., Zhao, Z., Zhang, S., Zhang, M., & Yang, J. (2020). FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2396-2409.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2946808.

Gao, C., Shi, L., Li, Q., Liu, K., Xue, C.J., Yang, J., & Zhang, Y. (2020). Aging Capacitor Supported Cache Management Scheme for Solid-State Drives. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2230-2239.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2949541.

Gao, C., Shi, L., Liu, K., Xue, C.J., Yang, J., & Zhang, Y. (2020). Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 31(9), 2185-2200.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2020.2987894.

Li, C., Zigerelli, A., Yang, J., Zhang, Y., Ma, S., & Guo, Y. (2020). A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(1), 75-87.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2018.2883906.

Wen, W., Zhao, L., Zhang, Y., & Yang, J. (2020). Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 39(10), 2347-2360.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2019.2940685.

Li, C., Sun, Y., Jin, L., Xu, L., Cao, Z., Fan, P., Kaeli, D., Ma, S., Guo, Y., & Yang, J. (2019). Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems. IEEE COMPUTER ARCHITECTURE LETTERS, 18(2), 157-160.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2019.2955119.

Pan, J., Ding, S., Wu, D., Yang, S., & Yang, J. (2019). Exploring behavioural intentions toward smart healthcare services among medical practitioners: a technology transfer perspective. INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 57(18), 5801-5820.Taylor & Francis. doi: 10.1080/00207543.2018.1550272.

Cui, J., Zhang, Y., Shi, L., Xue, C.J., Wu, W., & Yang, J. (2018). ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(10), 1957-1970.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2017.2782765.

Cui, J., Zhang, Y., Wu, W., Yang, J., Wang, Y., & Huang, J. (2018). DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(8), 1546-1559.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2017.2766156.

Wang, C., Wei, Q., Wu, L., Wang, S., Chen, C., Xiao, X., Yang, J., Xue, M., & Yang, Y. (2018). Persisting RB-Tree into NVM in a Consistency Perspective. ACM Transactions on Storage, 14(1), 1-27.Association for Computing Machinery (ACM). doi: 10.1145/3177915.

Wang, C., Wei, Q., Yang, J., Chen, C., Yang, Y., & Xue, M. (2018). NV-Dedup: High-Performance Inline Deduplication for Non-Volatile Memory. IEEE Transactions on Computers, 67(5), 658-671.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tc.2017.2774270.

Wang, R., Mittal, S., Zhang, Y., & Yang, J. (2017). Decongest: Accelerating Super-Dense PCM Under Write Disturbance by Hot Page Remapping. IEEE COMPUTER ARCHITECTURE LETTERS, 16(2), 107-110.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2017.2675883.

Wen, W., Yang, J., & Zhang, Y. (2017). Optimizing power efficiency for 3D stacked GPU-in-memory architecture. MICROPROCESSORS AND MICROSYSTEMS, 49, 44-53.Elsevier. doi: 10.1016/j.micpro.2017.01.005.

Zhang, X., Zhang, Y., Childers, B.R., & Yang, J. (2017). On the Restore Time Variations of Future DRAM Memory. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 22(2), 1-24.Association for Computing Machinery (ACM). doi: 10.1145/2967609.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2016). Simultaneous Multikernel: Fine-Grained Sharing of GPUs. IEEE COMPUTER ARCHITECTURE LETTERS, 15(2), 113-116.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2015.2477405.

Yang, J., Wei, Q., Wang, C., Chen, C., Yong, K.L., & He, B. (2016). NV-Tree: A Consistent and Workload-Adaptive Tree Structure for Non-Volatile Memory. IEEE Transactions on Computers, 65(7), 2169-2183.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tc.2015.2479621.

Jiang, L., Zhao, B., Yang, J., & Zhang, Y. (2015). Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 20(4), 1-24.Association for Computing Machinery (ACM). doi: 10.1145/2764903.

Li, P., Luo, Y., & Yang, J. (2015). Transformer: Run-time reprogrammable heterogeneous architecture for transparent acceleration of dynamic workloads. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 86, 45-61.Elsevier. doi: 10.1016/j.jpdc.2015.08.002.

Wang, R., Jiang, L., Zhang, Y., & Yang, J. (2015). SD-PCM Constructing Reliable Super Dense Phase Change Memory under Write Disturbance. ACM SIGPLAN NOTICES, 50(4), 19-31.Association for Computing Machinery (ACM). doi: 10.1145/2694344.2694352.

Wei, Q., Chen, C., Xue, M., & Yang, J. (2015). Z-MAP. ACM Transactions on Storage, 11(1), 1-33.Association for Computing Machinery (ACM). doi: 10.1145/2629663.

Xu, Y., Zhao, B., Zhang, Y., & Yang, J. (2015). Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers. ACM Transactions on Parallel Computing, 2(1), 1-23.Association for Computing Machinery (ACM). doi: 10.1145/2742349.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2014). Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor (vol 62, pg 2252, 2013). IEEE TRANSACTIONS ON COMPUTERS, 63(2), 525-526.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2014.5.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2014). Erratum: Process variation-aware nonuniform cache management in a 3d die-stacked multicore processor (IEEE Transactions on Computers (2013) 62:11 (2252-2265)). IEEE Transactions on Computers, 63(2), 525-526. doi: 10.1109/TC.2014.5.

Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2014). Throughput Enhancement for Phase Change Memories. IEEE TRANSACTIONS ON COMPUTERS, 63(8), 2080-2093.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2013.76.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B.R., & Yang, J. (2013). Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(2), 1-25.Association for Computing Machinery (ACM). doi: 10.1145/2459316.2459318.

Jiang, L., Du, Y., Zhao, B., Zhang, Y., Childers, B.R., & Yang, J. (2013). Hardware-assisted cooperative integration of wear-leveling and salvaging for phase change memory. Transactions on Architecture and Code Optimization, 10(2). doi: 10.1145/2459316.2459.

Zhao, B., Du, Y., Yang, J., & Zhang, Y. (2013). Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor. IEEE TRANSACTIONS ON COMPUTERS, 62(11), 2252-2265.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2012.129.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2013). Common-Source-Line Array: An Area Efficient Memory Architecture for Bipolar Nonvolatile Devices. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 18(4), 1-18.Association for Computing Machinery (ACM). doi: 10.1145/2500459.

Lee, B.C., Zhou, P., Yang, J., Zhang, Y., Zhao, B., Ipek, E., Mutlu, O., & Burger, D. (2010). PHASE-CHANGE TECHNOLOGY AND THE FUTURE OF MAIN MEMORY. IEEE MICRO, 30(1), 131-141.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2010.24.

Xia, L., Zhu, Y., Yang, J., Ye, J., & Gu, Z. (2010). Implementing a Thermal-Aware Scheduler in Linux Kernel on a Multi-Core Processor. COMPUTER JOURNAL, 53(7), 895-903.Oxford University Press (OUP). doi: 10.1093/comjnl/bxp119.

Yang, J., Gao, L., Zhang, Y., Chrobak, M., & Lee, H.H.S. (2010). A low-cost memory remapping scheme for address bus protection. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 70(5), 443-457.Elsevier. doi: 10.1016/j.jpdc.2009.11.008.

Zhang, Y., Yang, J., Li, W., Wang, L., & Jin, L. (2010). An authentication scheme for locating compromised sensor nodes in WSNs. JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, 33(1), 50-62.Elsevier. doi: 10.1016/j.jnca.2009.06.003.

Zhang, Y., Yang, J., Vu, H.T., & Wu, Y. (2010). The design and evaluation of interleaved authentication for filtering false reports in multipath routing WSNs. WIRELESS NETWORKS, 16(1), 125-140.Springer Nature. doi: 10.1007/s11276-008-0119-0.

Zhou, X., Yang, J., Chrobak, M., & Zhang, Y. (2010). Performance-Aware Thermal Management via Task Scheduling. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 7(1). doi: 10.1145/1746065.1736070.

Zhou, X., Yang, J., Chrobak, M., & Zhang, Y. (2010). Performance-aware thermal management via task scheduling. ACM Transactions on Architecture and Code Optimization, 7(1), 1-31.Association for Computing Machinery (ACM). doi: 10.1145/1736065.1736070.

Zhou, X., Yang, J., Xu, Y., Zhang, Y., & Zhao, J. (2010). Thermal-Aware Task Scheduling for 3D Multicore Processors. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 21(1), 60-71.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2009.27.

Li, W., Zhang, Y., Yang, J., & Zheng, J. (2009). Towards Update-Conscious Compilation for Energy-Efficient Code Dissemination in WSNs. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 6(4), 1-33.Association for Computing Machinery (ACM). doi: 10.1145/1596510.1596512.

Suresh, D., Agrawal, B., Yang, J., & Najjar, W. (2009). Energy-Efficient Encoding Techniques for Off-Chip Data Buses. ACM Transactions on Embedded Computing Systems, 8(2;9).

Suresh, D.C., Agrawal, B., Yang, J., & Najjar, W. (2009). Energy-Efficient Encoding Techniques for Off-Chip Data Buses. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 8(2), 1-23.Association for Computing Machinery (ACM). doi: 10.1145/1457255.1457256.

Suresh, D.C., Agrawal, B., Yang, J., & Najjar, W.A. (2009). Tunable and Energy Efficient Bus Encoding Techniques. IEEE TRANSACTIONS ON COMPUTERS, 58(8), 1049-1062.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2009.39.

Zhang, Y., Yang, J., & Gao, L. (2009). Supporting flexible streaming media protection through privacy-aware secure processors. COMPUTERS & ELECTRICAL ENGINEERING, 35(2), 286-299.Elsevier. doi: 10.1016/j.compeleceng.2008.06.001.

Luo, Y., Yu, J., Yang, J., & Bhuyan, L. (2007). Conserving Network Processor Power Consumption by Exploiting Traffic Variability. ACM Transactions on Architecture and Code Optimization, 4(1;4), 26 pages.

Luo, Y., Yu, J., Yang, J., & Bhuyan, L.N. (2007). Conserving network processor power consumption by exploiting traffic variability. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 4(1), 4-es.Association for Computing Machinery (ACM). doi: 10.1145/1216544.1216547.

Wu, W., Jin, L., Yang, J., Liu, P., & Tan, S. (2007). Efficient Power Modeling and Soft-ware Thermal Sensing for Runtime Temperature Monitoring. ACM Transactions on Design Automation of Electronic Systems, Special Issue on Demonstrable Software Systems and Hardware Plat-forms, 12(3;26), 29 pages.

Liu, P., Li, H., Jin, L., Wu, W., Tan, S.X.D., & Yang, J. (2006). Fast thermal simulation for runtime temperature tracking and management. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 25(12), 2882-2893.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCAD.2006.882594.

Yang, J., Gao, L., & Zhang, Y.T. (2005). Improving memory encryption performance in secure processors. IEEE TRANSACTIONS ON COMPUTERS, 54(5), 630-640.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2005.80.

Yang, J., Yu, J., & Zhang, Y.T. (2005). A low energy cache design for multimedia applications exploiting set access locality. JOURNAL OF SYSTEMS ARCHITECTURE, 51(10-11), 653-664.Elsevier. doi: 10.1016/j.sysarc.2005.02.003.

Zhang, C., Vahid, F., Yang, J., & Najjar, W. (2005). A way-halting cache for low-energy high-performance systems. ACM Transactions on Architecture and Code Optimization, 2(1), 34-54.Association for Computing Machinery (ACM). doi: 10.1145/1061267.1061270.

Zhang, Y., & Yang, J. (2005). Reducing I-cache Energy of Multimedia Applications through Low Cost Tag Comparison Elimination. Journal of Embedded Computing, 1(4), 461-470.

Chen, X., Luo, Y., Hsieh, H., Bhuyan, L., & Balarin, F. (2004). Assertion based verification and analysis of network processor architectures. DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 9(3), 163-176.Springer Nature. doi: 10.1007/s10617-005-1193-5.

Luo, Y., Yang, J., Bhuyan, L.N., & Zhao, L. (2004). Nepsim: A network processor simulator with a power evaluation framework. IEEE MICRO, 24(5), 34-44.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2004.52.

Yang, J., Gupta, R., & Zhang, C.J. (2004). Frequent value encoding for low power data buses. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 9(3), 354-384.Association for Computing Machinery (ACM). doi: 10.1145/1013948.1013953.

Suresh, D.C., Yang, J., Zhang, C.J., Agrawal, B., & Najjar, W. (2003). FV-MSB: A scheme for reducing transition activity on data buses. HIGH PERFORMANCE COMPUTING - HIPC 2003, 2913, 44-54.Springer Nature. doi: 10.1007/978-3-540-24596-4_6.

Zhang, C., Vahid, F., Yang, J., & Walid, W. (2003). A Way-Halting Cache for Low-Energy High-Performance Systems. IEEE Computer Architecture Letters, 2(1), 5.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/l-ca.2003.2.

Yang, J., & Gupta, R. (2002). Frequent value locality and its applications. ACM Transactions on Embedded Computing Systems, 1(1), 79-105.Association for Computing Machinery (ACM). doi: 10.1145/581888.581894.

Tang, D., & Yang, J. (2000). Free Moving Boundary Model and Boundary Iteration Method for Unsteady Viscous Flow in Stenotic Elastic Tubes. SIAM Journal on Scientific Computing, 21(4), 1370-1386.

Zhang, Y., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. ACM SIGOPS Operating Systems Review, 34(5), 150-159.Association for Computing Machinery (ACM). doi: 10.1145/384264.379235.

Zhang, Y., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. ACM SIGPLAN Notices, 35(11), 150-159.Association for Computing Machinery (ACM). doi: 10.1145/356989.357003.

Tang, D., Yang, J., Yang, C., & Ku, D.N. (1999). A nonlinear axisymmetric model with fluid-wall interactions for steady viscous flow in stenotic elastic tubes. JOURNAL OF BIOMECHANICAL ENGINEERING-TRANSACTIONS OF THE ASME, 121(5), 494-501.ASME International. doi: 10.1115/1.2835078.

Yang, B., Chen, R., Huang, K., Yang, J., & Gao, W. (2022). Eavesdropping user credentials via GPU side channels on smartphones. In Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, (pp. 285-299).Association for Computing Machinery (ACM). doi: 10.1145/3503222.3507757.

Ganguly, D., Melhem, R., & Yang, J. (2021). An Adaptive Framework for Oversubscription Management in CPU-GPU Unified Memory. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 00, (pp. 1212-1217).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.23919/date51398.2021.9473982.

Gao, C., Xin, X., Lu, Y., Zhang, Y., Yang, J., & Shu, J. (2021). ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory based SSDs. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 59-70).Association for Computing Machinery (ACM). doi: 10.1145/3466752.3480078.

Guo, Y., Zigerelli, A., Zhang, Y., & Yang, J. (2021). IVcache. In Proceedings of the 2021 Great Lakes Symposium on VLSI, (pp. 403-408).Association for Computing Machinery (ACM). doi: 10.1145/3453688.3461481.

Xin, X., Guo, Y., Zhang, Y., & Yang, J. (2021). SAM: Accelerating Strided Memory Accesses. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 324-336).Association for Computing Machinery (ACM). doi: 10.1145/3466752.3480091.

Ganguly, D., Zhang, Z., Yang, J., & Melhem, R. (2020). Adaptive Page Migration for Irregular Data-intensive Applications under GPU Memory Oversubscription. In 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 00, (pp. 451-461).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps47924.2020.00054.

Nie, S., Zhang, Y., Wu, W., & Yang, J. (2020). Layer RBER Variation Aware Read Performance Optimization for 3D Flash Memories. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 00, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dac18072.2020.9218631.

Tang, X., Zhang, Z., Xu, W., Kandemir, M.T., Melhem, R., & Yang, J. (2020). Enhancing Address Translations in Throughput Processors via Compression. In Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques, (pp. 191-204).Association for Computing Machinery (ACM). doi: 10.1145/3410463.3414633.

Wen, W., Zhang, Y., & Yang, J. (2020). Accelerating 3D vertical resistive memories with opportunistic write latency reduction. In Proceedings of the 39th International Conference on Computer-Aided Design, 2020-November, (pp. 1-8).Association for Computing Machinery (ACM). doi: 10.1145/3400302.3415677.

Xin, X., Zhang, Y., & Yang, J. (2020). ELP2IM: Efficient and Low Power Bitwise Operation Processing in DRAM. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 00, (pp. 303-314).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca47549.2020.00033.

Xin, X., Zhang, Y., & Yang, J. (2020). Reducing DRAM Access Latency via Helper Rows. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 00, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dac18072.2020.9218719.

Zhao, L., Zhang, Y., & Yang, J. (2020). SCA: A Secure CNN Accelerator for Both Training and Inference. In 2020 57th ACM/IEEE Design Automation Conference (DAC), 00, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dac18072.2020.9218752.

Deng, Q., Zhang, Y., Zhang, M., & Yang, J. (2019). LAcc. In Proceedings of the 56th Annual Design Automation Conference 2019, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3316781.3317845.

Ganguly, D., Zhang, Z., Yang, J., & Melhem, R. (2019). Interplay between hardware prefetcher and page eviction policy in CPU-GPU unified virtual memory. In Proceedings of the 46th International Symposium on Computer Architecture, (pp. 224-235).Association for Computing Machinery (ACM). doi: 10.1145/3307650.3322224.

Gao, C., Shi, L., Xue, C.J., Ji, C., Yang, J., & Zhang, Y. (2019). Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs. In 2019 35th Symposium on Mass Storage Systems and Technologies (MSST), 00, (pp. 172-184).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/msst.2019.000-5.

Gao, C., Ye, M., Li, Q., Xue, C.J., Zhang, Y., Shi, L., & Yang, J. (2019). Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 493-505).Association for Computing Machinery (ACM). doi: 10.1145/3352460.3358323.

Li, C., Ausavarungnirun, R., Rossbach, C.J., Zhang, Y., Mutlu, O., Guo, Y., & Yang, J. (2019). A Framework for Memory Oversubscription Management in Graphics Processing Units. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, (pp. 49-63).Association for Computing Machinery (ACM). doi: 10.1145/3297858.3304044.

Li, Q., Shi, L., Yang, J., Zhang, Y., & Xue, C.J. (2019). Leveraging Approximate Data for Robust Flash Storage. In Proceedings of the 56th Annual Design Automation Conference 2019, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3316781.3317848.

Liu, L., Wang, R., Zhang, Y., & Yang, J. (2019). H-ORAM. In Proceedings of the 56th Annual Design Automation Conference 2019, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3316781.3317841.

Nie, S., Zhang, Y., Wu, W., Zhang, C., & Yang, J. (2019). DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs. In 2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), 00, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nvmsa.2019.8863520.

Raoufi, M., Deng, Q., Zhang, Y., & Yang, J. (2019). PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 00, (pp. 82-87).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isvlsi.2019.00023.

Wen, W., Zhang, Y., & Yang, J. (2019). ReNEW: Enhancing Lifetime for ReRAM Crossbar based Neural Network Accelerators. In 2019 IEEE 37th International Conference on Computer Design (ICCD), 00, (pp. 487-496).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd46524.2019.00074.

Xin, X., Zhang, Y., & Yang, J. (2019). ROC. In Proceedings of the 56th Annual Design Automation Conference 2019, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3316781.3317900.

Zhang, X., Wang, R., Zhang, Y., & Yang, J. (2019). Boosting Chipkill Capability Under Retention-Error Induced Reliability Emergency. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, 00, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3287624.3287639.

Zhao, L., Deng, Q., Zhang, Y., & Yang, J. (2019). RFAcc. In Proceedings of the ACM International Conference on Supercomputing, (pp. 473-483).Association for Computing Machinery (ACM). doi: 10.1145/3330345.3330387.

Cui, J., Zhang, Y., Huang, J., Wu, W., & Yang, J. (2018). ShadowGC: Cooperative Garbage Collection with Multi-Level Buffer for Performance Improvement in NAND Flash-Based SSDs. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-January, (pp. 1247-1252).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.23919/date.2018.8342206.

Deng, Q., Jiang, L., Zhang, Y., Zhang, M., & Yang, J. (2018). DrAcc. In Proceedings of the 55th Annual Design Automation Conference, Part F137710, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3195970.3196029.

Garrett, T., Yang, J., & Zhang, Y. (2018). Enabling Intra-Plane Parallel Block Erase in NAND Flash to Alleviate the Impact of Garbage Collection. In Proceedings of the International Symposium on Low Power Electronics and Design, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3218603.3218627.

Li, C., Zigerelli, A., Yang, J., & Guo, Y. (2018). PEP. In Proceedings of the 55th Annual Design Automation Conference, Part F137710, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3195970.3196091.

Wang, R., Zhang, Y., & Yang, J. (2018). D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018-February, (pp. 416-427).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2018.00043.

Wen, W., Zhang, Y., & Yang, J. (2018). Wear leveling for crossbar resistive memory. In Proceedings of the 55th Annual Design Automation Conference, Part F137710, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/3195970.3196138.

Xu, Y., Yang, J., & Melhem, R. (2018). A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network. In ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 14(2), (pp. 1-23).Association for Computing Machinery (ACM). doi: 10.1145/3208073.

Chen, C., Yang, J., Wei, Q., Wang, C., & Xue, M. (2017). Optimizing File Systems with Fine-grained Metadata Journaling on Byte-addressable NVM. In ACM Transactions on Storage, 13(2), (pp. 1-25).Association for Computing Machinery (ACM). doi: 10.1145/3060147.

Deng, Q., Zhang, Y., Zhang, M., & Yang, J. (2017). Towards Warp-Scheduler Friendly STT-RAM/SRAM Hybrid GPGPU Register File Design. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 736-742).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2017.8203850.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2017). Quality of Service Support for Fine-Grained Sharing on GPUs. In Proceedings of the 44th Annual International Symposium on Computer Architecture, Part F128643, (pp. 269-281).Association for Computing Machinery (ACM). doi: 10.1145/3079856.3080203.

Wange†, R., Zhang§, Y., & Yangt†, J. (2017). Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server Settings. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), (pp. 325-336).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2017.9.

Wei, Q., Wang, C., Chen, C., Yang, Y., Yang, J., & Xue, M. (2017). Transactional NVM cache with high performance and crash consistency. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, (pp. 1-12).Association for Computing Machinery (ACM). doi: 10.1145/3126908.3126940.

Wen, W., Zhang, Y., & Yang, J. (2017). Read Error Resilient MLC STT-MRAM Based Last Level Cache. In 2017 IEEE International Conference on Computer Design (ICCD), (pp. 455-462).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2017.80.

Wen, W., Zhao, L., Zhang, Y., & Yang, J. (2017). Speeding Up Crossbar Resistive Memory by Exploiting In-Memory Data Patterns. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 261-267).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2017.8203787.

Zhang, X., Zhang, Y., Childers, B.R., & Yang, J. (2017). DrMP: Mixed Precision-Aware DRAM for High Performance Approximate and Precise Computing. In 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2017-September, (pp. 53-63).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/pact.2017.34.

Zhao, L., Jiang, L., Zhang, Y., Xiao, N., & Yang, J. (2017). Constructing Fast and Energy Efficient 1TnR Based ReRAM Crossbar Memory. In 2017 18th International Symposium on Quality Electronic Design (ISQED), (pp. 58-64).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isqed.2017.7918293.

Zhao, L., Zhang, Y., & Yang, J. (2017). Mitigating Shift-Based Covert-Channel Attacks in Racetrack Last Level Caches. In 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA), (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nvmsa.2017.8064476.

Zhao, L., Zhang, Y., & Yang, J. (2017). AEP: An Error-bearing Neural Network Accelerator for Energy Efficiency and Model Protection. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 765-771).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2017.8203854.

Zhao, L., Zhang, Y., & Yang, J. (2017). AEP: An Error-Bearing Neural Network Accelerator for Energy Efficiency and Model Protection. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 1047-1053).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2017.8203897.

Chen, C., Yang, J., Wei, Q., Wang, C., & Xue, M. (2016). Fine-Grained Metadata Journaling on NVM. In 2016 32nd Symposium on Mass Storage Systems and Technologies (MSST), 0, (pp. 1-13).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/msst.2016.7897077.

Wang, R., Zhang, Y., & Yang, J. (2016). ReadDuo: Constructing Reliable MLC Phase Change Memory Through Fast and Robust Readout. In 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), (pp. 203-214).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dsn.2016.27.

Wang, Z., Yang, J., Melhem, R., Childers, B., Zhang, Y., & Guo, M. (2016). Simultaneous Multikernel GPU: Multi-Tasking Throughput Processors via Fine-Grained Sharing. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016-April, (pp. 358-369).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2016.7446078.

Wei, Q., Chen, C., Xue, M., Wang, C., & Yang, J. (2016). Extending SSD Lifetime with Persistent In-memory Metadata Management. In 2016 IEEE International Conference on Cluster Computing (CLUSTER), (pp. 308-311).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/cluster.2016.45.

Xue, M., Wang, C., Wei, Q., Yang, J., & Chen, C. (2016). NVM-Accelerated Metadata Management for Flash-Based SSDs. In 2016 International Conference on Cloud Computing Research and Innovations (ICCCRI), (pp. 134-139).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icccri.2016.28.

Zhang, X., Zhang, Y., Childers, B., & Yang, J. (2016). AWARD. In Proceedings of the Second International Symposium on Memory Systems, 03-06-October-2016, (pp. 322-324).Association for Computing Machinery (ACM). doi: 10.1145/2989081.2989127.

Zhanq, X., Zhang, Y., Childers, B.R., & Yang, J. (2016). Restore Truncation for Performance Improvement in Future DRAM Systems. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016-April, (pp. 543-554).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2016.7446093.

Childers, B.R., Yang, J., & Zhang, Y. (2015). Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes. In Proceedings of the 2015 International Symposium on Memory Systems, 05-08-October-2015, (pp. 78-84).Association for Computing Machinery (ACM). doi: 10.1145/2818950.2818963.

Liu, J., Yang, J., & Melhem, R. (2015). Gasolin: Global Arbitration for Streams of Data in Optical Links. In 2015 IEEE International Parallel and Distributed Processing Symposium, (pp. 93-102).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2015.61.

Liu, J., Yang, J., & Melhem, R. (2015). SAWS. In Proceedings of the 48th International Symposium on Microarchitecture, 05-09-December-2015, (pp. 383-394).Association for Computing Machinery (ACM). doi: 10.1145/2830772.2830822.

Wang, C., Wei, Q., Xue, M., Yang, J., & Chen, C. (2015). Data-Centric Garbage Collection for NAND Flash Devices. In 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA), (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nvmsa.2015.7304360.

Wang, C., Wei, Q., Yang, J., Chen, C., & Xue, M. (2015). How to Be Consistent with Persistent Memory? An Evaluation Approach. In 2015 IEEE International Conference on Networking, Architecture and Storage (NAS), (pp. 186-194).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nas.2015.7255223.

Wang, R., Jiang, L., Zhang, Y., Wang, L., & Yang, J. (2015). Selective restore. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/2744769.2744908.

Wang, R., Jiang, L., Zhang, Y., Wang, L., & Yang, J. (2015). Exploit imbalanced cell writes to mitigate write disturbance in dense phase change memory. In Proceedings of the 52nd Annual Design Automation Conference, 2015-July, (pp. 1-6).Association for Computing Machinery (ACM). doi: 10.1145/2744769.2744841.

Wei, Q., Xue, M., Yang, J., Wang, C., & Cheng, C. (2015). Accelerating Cloud Storage System with Byte-Addressable Non-Volatile Memory. In 2015 IEEE 21st International Conference on Parallel and Distributed Systems (ICPADS), 2016-January, (pp. 354-361).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icpads.2015.52.

Xu, Y., Yang, J., & Melhem, R. (2015). BandArb. In Proceedings of the 12th ACM International Conference on Computing Frontiers, (pp. 1-8).Association for Computing Machinery (ACM). doi: 10.1145/2742854.2742876.

Yang, J., Wei, Q., Chen, C., Wang, C., Yong, K.L., & He, B. (2015). NV-Tree: Reducing consistency cost for NVM-based single level systems. In Proceedings of the 13th USENIX Conference on File and Storage Technologies, FAST 2015, (pp. 167-181).

Zhang, X., Zhang, Y., & Yang, J. (2015). DLB: Dynamic Lane Borrowing for Improving Bandwidth and Performance in Hybrid Memory Cube. In 2015 33rd IEEE International Conference on Computer Design (ICCD), (pp. 125-132).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2015.7357093.

Zhang, X., Zhang, Y., & Yang, J. (2015). TriState-SET: Proactive SET for Improved Performance of MLC Phase Change Memories. In 2015 33rd IEEE International Conference on Computer Design (ICCD), (pp. 659-665).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2015.7357178.

Zhang, X., Zhang, Y., Childers, B.R., & Yang, J. (2015). Exploiting DRAM Restore Time Variations in Deep Sub-micron Scaling. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, 2015-April, (pp. 477-482).EDAA. doi: 10.7873/date.2015.0969.

Zhang, X., Zhao, L., Zhang, Y., & Yang, J. (2015). Exploit Common Source-Line to Construct Energy Efficient Domain Wall Memory Based Caches. In 2015 33rd IEEE International Conference on Computer Design (ICCD), (pp. 157-163).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2015.7357097.

Jiang, L., Zhang, Y., & Yang, J. (2014). Mitigating Write Disturbance in Super Dense Phase Change Memories. In 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, (pp. 216-227).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dsn.2014.32.

Jiang, L., Zhao, B., Yang, J., & Zhang, Y. (2014). A Low Power and Reliable Charge Pump Design for Phase Change Memories. In 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), (pp. 397-408).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isca.2014.6853194.

Wei, Q., Chen, C., & Yang, J. (2014). CBM: A cooperative buffer management for SSD. In 2014 30th Symposium on Mass Storage Systems and Technologies (MSST), (pp. 1-12).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/msst.2014.6855545.

Guo, J., Yang, J., Zhang, Y., & Cheri, Y. (2013). Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (pp. 859-864).EDAA. doi: 10.7873/date.2013.181.

Zhang, X., Jiang, L., Zhang, Y., Chuanjun, Z., & Yang, J. (2013). WoM-SET: Low Power Proactive-SET-based PCM Write using WoM Code. In International Symposium on Low Power Electronics and Design (ISLPED), (pp. 217-222).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/islped.2013.6629297.

Zhao, B., Zhang, Y., & Yang, J. (2013). A Speculative Arbiter Design to Enable High-Frequency Many-VC Router in NoCs. In 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nocs.2013.6558415.

Zhou, P., Zhang, Y., & Yang, J. (2013). The Design of Sustainable Wireless Sensor Network Node using Solar Energy and Phase Change Memory. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (pp. 869-872).EDAA. doi: 10.7873/date.2013.183.

Jiang, L., Zhang, Y., & Yang, J. (2012). ER. In Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, (pp. 39-44).Association for Computing Machinery (ACM). doi: 10.1145/2333660.2333672.

Jiang, L., Zhang, Y., Childers, B.R., & Yang, J. (2012). FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory. In 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 1-12).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/micro.2012.10.

Jiang, L., Zhao, B., Zhang, Y., & Yang, J. (2012). Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors. In Proceedings of the 49th Annual Design Automation Conference, (pp. 907-912).Association for Computing Machinery (ACM). doi: 10.1145/2228360.2228521.

Jiang, L., Zhao, B., Zhang, Y., †, J.Y., & Childers, B.R. (2012). Improving Write Operations in MLC Phase Change Memory. In IEEE International Symposium on High-Performance Comp Architecture, (pp. 1-10).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2012.6169027.

Xu, Y., Yang, J., & Melhem, R. (2012). Tolerating Process Variations in Nanophotonic On-chip Networks*This work is supported in part by NSF 0747242 and 1012070. In 2012 39th Annual International Symposium on Computer Architecture (ISCA), 1, (pp. 142-152).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isca.2012.6237013.

Xu, Y., Yang, J., & Melhem, R. (2012). Channel borrowing. In Proceedings of the 26th ACM international conference on Supercomputing, (pp. 133-142).Association for Computing Machinery (ACM). doi: 10.1145/2304576.2304595.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2012). Architecting a common-source-line array for bipolar non-volatile memory devices. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1451-1454).

Jiang, L., Du, Y., Zhang, Y., Childers, B.R., & Yang, J. (2011). LLS: Cooperative Integration of Wear-Leveling and Salvaging for PCM Main Memory. In 2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks (DSN), (pp. 221-232).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dsn.2011.5958221.

Jiang, L., Zhang, Y., & Yang, J. (2011). Enhancing Phase Change Memory Lifetime through Fine-Grained Current Regulation and Voltage Upscaling. In IEEE/ACM International Symposium on Low Power Electronics and Design, (pp. 127-132).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/islped.2011.5993624.

Li, L., Zhang, Y., & Yang, J. (2011). Proactive recovery for BTI in high-k SRAM cells. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 992-997).

Xu, Y., Du, Y., Zhang, Y., & Yang, J. (2011). A composite and scalable cache coherence protocol for large scale CMPs. In Proceedings of the international conference on Supercomputing, (pp. 285-294).Association for Computing Machinery (ACM). doi: 10.1145/1995896.1995941.

Zhou, P., Zhao, B., Zhang, Y., Yang, J., & Chen, Y. (2011). MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement. In 2011 International Conference on Parallel Architectures and Compilation Techniques, 1, (pp. 207-208).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/pact.2011.29.

Li, L., Zhang, Y., Yang, J., & Zhao, J. (2010). Proactive NBTI mitigation for busy functional units in out-of-order microprocessors. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 411-416).

Xu, Y., Zhao, B., Zhang, Y., & Yang, J. (2010). Simple Virtual Channel Allocation for High Throughput and High Frequency On-Chip Routers*. In HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, 1, (pp. 1-11).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2010.5416640.

Zhou, P., Du, Y., Zhang, Y., & Yang, J. (2010). Fine-Grained QoS Scheduling for PCM-based Main Memory Systems. In 2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), (pp. 1-12).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2010.5470451.

Xu, Y., Du, Y., Zhao, B., Zhou, X., Zhang, Y., & Yang, J. (2009). A Low-Radix and Low-Diameter 3D Interconnection Network Design. In 2009 IEEE 15th International Symposium on High Performance Computer Architecture, 1, (pp. 30-42).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2009.4798234.

Zhao, B., Du, Y., Zhang, Y., & Yang, J. (2009). Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, (pp. 222-231).Association for Computing Machinery (ACM). doi: 10.1145/1669112.1669141.

Zhou, P., Zhao, B., Du, Y., Xu, Y., Zhang, Y., Yang, J., & Zhao, L. (2009). Frequent Value Compression in Packet-based NoC Architectures. In 2009 Asia and South Pacific Design Automation Conference, 1, (pp. 13-18).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/aspdac.2009.4796434.

Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2009). Energy reduction for STT-RAM using early write termination. In Proceedings of the 2009 International Conference on Computer-Aided Design, (pp. 264-268).Association for Computing Machinery (ACM). doi: 10.1145/1687399.1687448.

Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2009). A durable and energy efficient main memory using phase change memory technology. In Proceedings of the 36th annual international symposium on Computer architecture, (pp. 14-23).Association for Computing Machinery (ACM). doi: 10.1145/1555754.1555759.

Yang, J., Zhou, X., Chrobak, M., Zhang, Y., & Jin, L. (2008). Dynamic Thermal Management through Task SchedulingBehaviors*This work is supported in part by NSF grants CCF-0734339, CNS-0720595, OISE-0340752 and CCF-0641177. In ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software, (pp. 191-201).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ispass.2008.4510751.

Zhou, X., Xu, Y., Du, Y., Zhang, Y., & Yang, J. (2008). Thermal Management for 3D Processors via Task Scheduling *This work is supported in part by NSF grants CCF-0734339, CNS-0720595, CAREER 0747242, and CAREER 0641177. In 2008 37th International Conference on Parallel Processing, (pp. 115-122).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icpp.2008.51.

Li, W., Zhang, Y., Yang, J., & Zheng, J. (2007). UCC: Update-conscious compilation for energy efficiency in wireless sensor networks. In ACM SIGPLAN NOTICES, 42(6), (pp. 383-393).Association for Computing Machinery (ACM). doi: 10.1145/1273442.1250778.

Wu, W., Yang, J., Tan, S.X.D., & Lu, S.L. (2007). Improving the Reliability of On-Chip Data Caches Under Process Variations. In 2007 25th International Conference on Computer Design, (pp. 325-332).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2007.4601920.

Yu, J., Yao, J., Bhuyan, L., & Yang, J. (2007). Program Mapping onto Network Processors by Recursive Bipartitioning and Refining. In 2007 44th ACM/IEEE Design Automation Conference, (pp. 805-810).IEEE. doi: 10.1109/dac.2007.375275.

Gao, L., Yang, J., Chrobak, M., Zhang, Y., Nguyen, S., & Lee, H.H.S. (2006). A low-cost memory remapping scheme for address bus protection. In Proceedings of the 15th international conference on Parallel architectures and compilation techniques, 2006, (pp. 74-83).Association for Computing Machinery (ACM). doi: 10.1145/1152154.1152169.

Jin, L., Wu, W., Yang, J., Zhang, C., & Zhang, Y. (2006). Reduce Register Files Leakage Through Discharging Cells. In Proceedings International Conference on Computer Design VLSI in Computers and Processors, (pp. 114-119).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2006.4380803.

Li, W., Zhang, Y., & Yang, J. (2006). Dynamic Authentication-Key Re-assignment for Reliable Report Delivery. In 2006 IEEE International Conference on Mobile Ad Hoc and Sensor Sysetems, 1, (pp. 467-476).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mobhoc.2006.278587.

Shi, W., Fryman, J.B., Gu, G., Lee, H.H.S., Zhang, Y., & Yang, J. (2006). InfoShield: A Security Architecture for Protecting Information Usage in Memory. In The Twelfth International Symposium on High-Performance Computer Architecture, 2006., 2006, (pp. 225-234).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2006.1598131.

Wu, W., Jin, L., Yang, J., Liu, P., & Tan, S.X.D. (2006). A systematic method for functional unit power estimation in microprocessors. In Proceedings of the 43rd annual conference on Design automation - DAC '06, (pp. 554-557).Association for Computing Machinery (ACM). doi: 10.1145/1146909.1147053.

Zhang, Y., Yang, J., & Vu, H.T. (2006). The Interleaved Authentication for Filtering False Reports in Multipath Routing based Sensor Networks. In Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006, (pp. 1-10).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2006.1639330.

Zhang, Y., Yang, J., Jin, L., & Li, W. (2006). Locating compromised sensor nodes through incremental hashing authentication. In DISTRIBUTED COMPUTING IN SENSOR SYSTEMS, PROCEEDINGS, 4026, (pp. 321-337).Springer Nature. doi: 10.1007/11776178_20.

Jin, L.L., Wu, W., Yang, J., Zhang, C.J., & Zhang, Y.T. (2005). Dynamic co-allocation of level one caches. In EMBEDDED SOFTWARE AND SYSTEMS, PROCEEDINGS, 3820, (pp. 373-385).Springer Nature. doi: 10.1007/11599555_36.

Li, H., Liu, P., Qi, Z., Jin, L., Wu, W., Tan, S.X.D., & Yang, F. (2005). Efficient thermal simulation for run-time temperature tracking and management. In 2005 International Conference on Computer Design, 2005, (pp. 130-133).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2005.46.

Lin, Y., Zhang, Y., Li, Q., & Yang, J. (2005). Supporting efficient query processing on compressed XML files. In Proceedings of the 2005 ACM symposium on Applied computing, 1, (pp. 660-665).Association for Computing Machinery (ACM). doi: 10.1145/1066677.1066827.

Liu, P., Qi, Z., Li, H., Jin, L., Wu, W., Tan, S.X.D., & Yang, J. (2005). Fast Thermal Simulation for Architecture Level Dynamic Thermal Management ** This work is funded by NSF CAREER Award CCF-0448534, UC Senate Research Funds (05–06). In ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., 2005, (pp. 639-644).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2005.1560145.

Luo, Y., Yu, J., Yang, J., & Bhuyan, L. (2005). Low power network processor design using clock gating. In Proceedings of the 42nd annual conference on Design automation - DAC '05, (pp. 712-715).Association for Computing Machinery (ACM). doi: 10.1145/1065579.1065766.

Suresh, D.C., Agrawal, B., Najjar, W., & Yang, J. (2005). A tunable bus encoder for off-chip data buses. In ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005., (pp. 319-322).IEEE. doi: 10.1109/lpe.2005.195539.

Suresh, D.C., Agrawal, B., Najjar, W.A., & Yang, J. (2005). VALVE: Variable Length Value Encoder for Off-Chip Data Buses. In 2005 International Conference on Computer Design, 2005, (pp. 631-633).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2005.113.

Suresh, D.C., Najjar, W.A., & Yang, J. (2005). Power efficient instruction caches for embedded systems. In EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, 3553, (pp. 182-191).Springer Nature. doi: 10.1007/11512622_20.

Yu, J., Wu, W., Chen, X., Hsieh, H., Yang, J., & Balarin, F. (2005). Assertion-Based Design Exploration of DVS in Network Processor Architectures. In Design, Automation and Test in Europe, I, (pp. 92-97).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/date.2005.69.

Yu, J., Yang, J., Chen, S.J., Luo, Y., & Bhuyan, L. (2005). Enhancing network processor simulation speed with statistical input sampling. In HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS, PROCEEDINGS, 3793, (pp. 68-83).Springer Nature. doi: 10.1007/11587514_6.

Zhang, Y., Gao, L., Yang, J., Zhang, X., & Gupta, R. (2005). SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. In 11th International Symposium on High-Performance Computer Architecture, (pp. 352-362).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2005.31.

Yu, J., Wu, W., Chen, X., Hsieh, H., Yang, J., & Balarín, F. (2004). Assertion-Based Power/Performance Analysis of Network Processor Architectures. In Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940), (pp. 155-160).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hldvt.2004.1431261.

Zhang, C., Vahid, F., Yang, J., & Najjar, W. (2004). A Way-Halting Cache for Low-Energy High-Performance Systems. In Proceedings of the International Symposium on Low Power Electronics and Design, 2004-January(January), (pp. 126-131). doi: 10.1109/LPE.2004.240851.

Zhang, C., Vahid, F., Yang, J., & Najjar, W. (2004). A way-halting cache for low-energy high-performance systems. In Proceedings of the 2004 international symposium on Low power electronics and design, (pp. 126-131).Association for Computing Machinery (ACM). doi: 10.1145/1013235.1013272.

Zhang, C., Yang, J., & Vahid, F. (2004). Low static-power frequent-value data caches. In Proceedings - Design, Automation and Test in Europe Conference and Exhibition, 1, (pp. 214-219).

Suresh, D.C., Agrawal, B., Yang, J., Najjar, W., & Bhuyan, L. (2003). Power efficient encoding techniques for off-chip data buses. In Proceedings of the international conference on Compilers, architectures and synthesis for embedded systems - CASES '03, (pp. 267-275).ACM Press. doi: 10.1145/951741.951745.

Yang, J., Gao, L., & Zhang, Y. (2003). Fast Secure Processor for Inhibiting Software Piracy and Tampering. In 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), 2003-January, (pp. 351-360).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/micro.2003.1253209.

Zhang, Y., & Yang, J. (2003). Low cost instruction cache designs for tag comparison elimination. In Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03, (pp. 266-269).ACM Press. doi: 10.1145/871568.871572.

Zhang, Y., & Yang, J. (2003). Procedural Level Address Offset Assignment of DSP Applications with Loops. In 2003 International Conference on Parallel Processing, 2003. Proceedings., 2003-January, (pp. 21-28).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icpp.2003.1240562.

Yang, J., & Gupta, R. (2002). Energy Efficient Frequent Value Data Cache Design**Supported by DARPA award no. F29601-00-1-0183 and National Science Foundation grants CCR-0208756 CCR-0220334, CCR-0105355, and EIA-0080123 to the University of Arizona. In 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings., 2002-January, (pp. 197-207).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/micro.2002.1176250.

Yang, J., & Gupta, R. (2001). Energy-efficient load and store reuse. In Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01, (pp. 72-75).Association for Computing Machinery (ACM). doi: 10.1145/383082.383097.

Yang, J., & Gupta, R. (2001). FV encoding for low-power data I/O. In Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01, (pp. 84-87).Association for Computing Machinery (ACM). doi: 10.1145/383082.383100.

Yang, J., & Gupta, R. (2000). Load redundancy removal through instruction reuse. In 2013 42nd International Conference on Parallel Processing, 2000-January, (pp. 61-68).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icpp.2000.876075.

Yang, J., Zhang, Y., & Gupta, R. (2000). Frequent value compression in data caches. In Proceedings of the 28th Annual International Symposium on Microarchitecture, (pp. 258-265).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/micro.2000.898076.

Zhang, Y.T., Yang, J., & Gupta, R. (2000). Frequent value locality and value-centric data cache design. In ACM SIGPLAN NOTICES, 35(11), (pp. 150-159).Association for Computing Machinery (ACM). doi: 10.1145/356989.357003.