Alex Jones

Ph.D., Electrical and Computer Engineering, Northwestern University, 2002

M.Sc., Computer-aided design and Parallel FPGA design, Northwestern University, 2000

B.Sc., Physics, The College of William and Mary, 1998

McKinney, E., Hatridge, M., & Jones, A.K. (2024). MIRAGE: Quantum Circuit Decomposition and Routing Collaborative Design Using Mirror Gates. 2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 00, 704-718.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca57654.2024.00060.

Zhuang, J., Lau, J., Ye, H., Yang, Z., Ji, S., Lo, J., Denolf, K., Neuendorffer, S., Jones, A., Hu, J., Shi, Y., Chen, D., Cong, J., & Zhou, P. (2024). CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. ACM Transactions on Reconfigurable Technology and Systems, 17(3), 1-31.Association for Computing Machinery (ACM). doi: 10.1145/3686163.

Dutta, P., Lee, A., Wang, K.L., Jones, A.K., & Bhanja, S. (2023). A Multi-Domain Magneto Tunnel Junction for Racetrack Nanowire Strips. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 22, 581-583.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TNANO.2023.3298920.

Khan, A.A., Ollivier, S., Hameed, F., Castrillon, J., & Jones, A.K.K. (2023). DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories. IEEE TRANSACTIONS ON COMPUTERS, 72(9), 2585-2599.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2023.3257509.

McKinney, E., Xia, M., Zhou, C., Lu, P., Hatridge, M., & Jones, A.K. (2023). Co-Designed Architectures for Modular Superconducting Quantum Computers. 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 00, 759-772.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca56546.2023.10071036.

McKinney, E., Zhou, C., Xia, M., Hatridge, M., & Jones, A.K. (2023). Parallel Driving for Fast Quantum Computing Under Speed Limits. Proceedings of the 50th Annual International Symposium on Computer Architecture, 1-13.Association for Computing Machinery (ACM). doi: 10.1145/3579371.3589075.

Ollivier, S., Li, S., Tang, Y., Cahoon, S., Caginalp, R., Chaudhuri, C., Zhou, P., Tang, X., Hu, J., & Jones, A.K. (2023). Sustainable AI Processing at the Edge. IEEE MICRO, 43(1), 19-28.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2022.3220399.

Ollivier, S., Longofono, S., Dutta, P., Hu, J., Bhanja, S., & Jones, A.K. (2023). Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT. IEEE TRANSACTIONS ON COMPUTERS, 72(4), 1095-1109.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2022.3188206.

Hameed, F., Khan, A.A., Ollivier, S., Jones, A.K., & Castrillon, J. (2022). DNA Pre-Alignment Filter Using Processing Near Racetrack Memory. IEEE COMPUTER ARCHITECTURE LETTERS, 21(2), 53-56.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2022.3194263.

Hogue, A., Jones, A.K., & Bhanja, S. (2022). XDWM: A 2D Domain Wall Memory. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 21, 185-188.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TNANO.2022.3158889.

Khan, A.A., Ollivier, S., Longofono, S., Hempel, G., Castrillon, J., & Jones, A.K. (2022). Brain-inspired Cognition in Next-generation Racetrack Memories. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 21(6), 1-28.Association for Computing Machinery (ACM). doi: 10.1145/3524071.

Ollivier, S., Zhang, X., Tang, Y., Choudhuri, C., Hu, J., & Jones, A.K. (2022). FPIRM: Floating-point Processing in Racetrack Memories.

Ollivier, S., Zhang, X., Tang, Y., Choudhuri, C., Hu, J., & Jones, A.K. (2022). Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge. IEEE MICRO, 42(6), 9-16.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MM.2022.3195761.

Roxy, K., Longofono, S., Olliver, S., Bhanja, S., & Jones, A.K. (2022). Pinning Fault Mode Modeling for DWM Shifting. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 69(7), 3319-3323.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCSII.2022.3161594.

Longofono, S., Kline, D., Melhem, R., & Jones, A.K. (2021). A CASTLE With TOWERs for Reliable, Secure Phase-Change Memory. IEEE TRANSACTIONS ON COMPUTERS, 70(9), 1311-1324.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2020.3006852.

Longofono, S., Kline, D.J., Melhem, R., & Jones, A.K. (2021). Predicting and mitigating single-event upsets in DRAM using HOTH. MICROELECTRONICS RELIABILITY, 117, 114024.Elsevier. doi: 10.1016/j.microrel.2020.114024.

Longofono, S., Seyedzadeh, S.M., & Jones, A.K. (2021). Virtual Coset Coding for Encrypted Non-Volatile Memories with Multi-Level Cells.

Ollivier, S., Longofono, S., Dutta, P., Hu, J., Bhanja, S., & Jones, A.K. (2021). PIRM: Processing In Racetrack Memories.

Roxy, K., Ollivier, S., Hoque, A., Longofono, S., Jones, A.K., & Bhanja, S. (2020). A Novel Transverse Read Technique for Domain-Wall "Racetrack" Memories. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 19, 648-652.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TNANO.2020.3014091.

Seyedzadeh, S.M., Kline, D.J., Jones, A.K., & Melhem, R. (2020). Sustainable disturbance crosstalk mitigation in deeply scaled phase-change memory. SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS, 28, 100410.Elsevier. doi: 10.1016/j.suscom.2020.100410.

Kline, D.J., Parshook, N., Ge, X., Brunvand, E., Melhem, R., Chrysanthis, P.K., & Jones, A.K. (2019). GreenChip: A tool for evaluating holistic sustainability of modern computing systems. SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS, 22, 322-332.Elsevier. doi: 10.1016/j.suscom.2017.10.001.

Zhang, J., Kline, D.J., Fang, L., Melhem, R., & Jones, A.K. (2019). Yielding optimized dependability assurance through bit inversion. INTEGRATION-THE VLSI JOURNAL, 64, 105-113.Elsevier. doi: 10.1016/j.vlsi.2018.09.002.

Kline, D.J., Melhem, R., & Jones, A.K. (2018). Counter Advance for Reliable Encryption in Phase Change Memory. IEEE COMPUTER ARCHITECTURE LETTERS, 17(2), 209-212.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2018.2861012.

Kline, D.J., Xu, H., Melhem, R., & Jones, A.K. (2018). Racetrack Queues for Extremely Low-Energy FIFOs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 26(8), 1531-1544.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2018.2819945.

Zhang, J., Kline, D.J., Fang, L., Melhem, R., & Jones, A.K. (2018). RETROFIT: Fault-Aware Wear Leveling. IEEE COMPUTER ARCHITECTURE LETTERS, 17(2), 167-170.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2018.2840137.

Zhang, J., Kline, D.J., Fang, L., Melhem, R., & Jones, A.K. (2018). Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 26(11), 2358-2371.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2018.2858186.

Ahson, S.A., & Ilyas, M. (2017). RFID Handbook. In RFID Handbook: Applications, Technology, Security, and Privacy, Ahson, S., & Ilyas, M. (Eds.). (pp. 199-230).CRC Press. doi: 10.1201/9781420055009.

Seyedzadeh, S.M., Jones, A.K., & Melhem, R. (2017). Counter-Based Tree Structure for Row Hammering Mitigation in DRAM. IEEE COMPUTER ARCHITECTURE LETTERS, 16(1), 18-21.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/LCA.2016.2614497.

Moeng, M., Jones, A.K., & Melhem, R.G. (2016). Weighted-Tuple: Fast and Accurate Synchronization for Parallel Architecture Simulators. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 27(8), 2462-2474.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2015.2494589.

Seyedzadeh, S.M., Maddah, R., Kline, D.J., Jones, A.K., & Melhem, R. (2016). Improving Bit Flip Reduction for Biased and Random Data. IEEE TRANSACTIONS ON COMPUTERS, 65(11), 3345-3356.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2016.2525982.

Xu, H., Alkabani, Y., Melhem, R., & Jones, A.K. (2016). FusedCache: A Naturally Inclusive, Racetrack Memory, Dual-Level Private Cache. IEEE Transactions on Multi-Scale Computing Systems, 2(2), 69-82.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmscs.2016.2536020.

Xu, H., Collinge, W.O., Schaefer, L.A., Landis, A.E., Bilec, M.M., & Jones, A.K. (2016). Towards a commodity solution for the internet of things. COMPUTERS & ELECTRICAL ENGINEERING, 52, 138-156.Elsevier. doi: 10.1016/j.compeleceng.2016.03.009.

Zhang, Y., Li, Y., Sun, Z., Li, H., Chen, Y., & Jones, A.K. (2015). Read Performance: The Newest Barrier in Scaled STT-RAM. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 23(6), 1170-1174.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2014.2326797.

Collinge, W., Landis, A.E., Jones, A.K., Schaefer, L.A., & Bilec, M.M. (2013). Indoor environmental quality in a dynamic life cycle assessment framework for whole buildings: Focus on human health chemical impacts. BUILDING AND ENVIRONMENT, 62, 182-190.Elsevier. doi: 10.1016/j.buildenv.2013.01.015.

Collinge, W.O., Landis, A.E., Jones, A.K., Schaefer, L.A., & Bilec, M.M. (2013). Dynamic life cycle assessment: framework and application to an institutional building. INTERNATIONAL JOURNAL OF LIFE CYCLE ASSESSMENT, 18(3), 538-552.Springer Nature. doi: 10.1007/s11367-012-0528-2.

Li, Y., Melhem, R., & Jones, A.K. (2013). PS-TLB: Leveraging Page Classification Information for Fast, Scalable and Efficient Translation for Future CMPs. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 9(4), 1-21.Association for Computing Machinery (ACM). doi: 10.1145/2400682.2400687.

Li, Y., Zhang, Y., Li, H., Chen, Y., & Jones, A. (2013). C1C: A Configurable, Compiler-guided STT-RAM L1 Cache. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) and ACM Transactions on Architecture and Code Optimization (TACO), 110(4), 52.

Li, Y., Zhang, Y., LI, H., Chen, Y., & Jones, A.K. (2013). C1C. ACM Transactions on Architecture and Code Optimization, 10(4), 1-22.Association for Computing Machinery (ACM). doi: 10.1145/2541228.2555308.

Saunders, C.L., Landis, A.E., Mecca, L.P., Jones, A.K., Schaefer, L.A., & Bilec, M.M. (2013). Analyzing the Practice of Life Cycle Assessment Focus on the Building Sector. JOURNAL OF INDUSTRIAL ECOLOGY, 17(5), 777-788.Wiley. doi: 10.1111/jiec.12028.

Thiel, C.L., Campion, N., Landis, A.E., Jones, A.K., Schaefer, L.A., & Bilec, M.M. (2013). A Materials Life Cycle Assessment of a Net-Zero Energy Building. ENERGIES, 6(2), 1125-1141.MDPI. doi: 10.3390/en6021125.

Abousamra, A., Jones, A.K., & Melhem, R. (2012). Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 23(6), 1038-1046.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2011.238.

Li, Y., Abousamra, A., Melhem, R., & Jones, A.K. (2012). Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 23(11), 2058-2066.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2011.279.

Li, Y., Melhem, R., & Jones, A.K. (2012). Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors. IEEE COMPUTER ARCHITECTURE LETTERS, 11(2), 49-52.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/L-CA.2011.35.

Li, Y., Zhang, Y., Chen, Y., & Jones, A.K. (2012). Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. IEEE Embedded Systems Letters, 4(4), 82-85.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/les.2012.2216253.

Dontharaju, S., Tung, S., Cain, J.T., Mats, L., Mickle, M.H., & Jones, A.K. (2009). A Design Automation and Power Estimation Flow for RFID Systems. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 14(1), 1-31.Association for Computing Machinery (ACM). doi: 10.1145/1455229.1455236.

Jones, A.K., Kerbyson, D.J., Rajamony, R., & Weems, C. (2009). Guest Editor's Note: Large-Scale Parallel Processing. Parallel Processing Letters, 19(4), 487-490.

JONES, A.K., KERBYSON, D.J., RAJAMONY, R., & WEEMS, C. (2009). GUEST EDITOR'S NOTE: LARGE SCALE PARALLEL PROCESSING. Parallel Processing Letters, 19(04), 487-490.World Scientific Publishing. doi: 10.1142/s0129626409000377.

Mehta, G., Stander, J., Baz, M., Hunsaker, B., & Jones, A.K. (2009). Interconnect Customization for a Hardware Fabric. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 14(1), 1-32.Association for Computing Machinery (ACM). doi: 10.1145/1455229.1455240.

Schaumont, P.R., Jones, A.K., & Trimberger, S. (2009). Guest Editors' Introduction to Security in Reconfigurable Systems Design. ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2(1), 1-6.Association for Computing Machinery (ACM). doi: 10.1145/1502781.1502782.

Shao, S., Jones, A.K., & Melhem, R. (2009). Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 20(3), 331-345.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TPDS.2008.82.

Zhang, Y., & Jones, A.K. (2009). Non-Uniform Fat-Meshes for Chip Multiprocessors * *This work is partially supported by NSF award number 0702452. 2009 IEEE International Symposium on Parallel & Distributed Processing, 19(4), 1-8.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2009.5161093.

Hoare, R.R., Ding, Z., & Jones, A.K. (2008). A two-stage hardware scheduler combining greedy and optimal scheduling. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 68(11), 1437-1451.Elsevier. doi: 10.1016/j.jpdc.2008.07.008.

Jones, A.K., & Walker, R. (2008). Introduction to the special section on demonstrable software systems and hardware platforms II. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 13(3), 1-3.Association for Computing Machinery (ACM). doi: 10.1145/1367045.1367047.

Jones, A.K., Dontharaju, S., Tung, S., Mats, L., Hawrylak, P.J., Hoare, R.R., Cain, J.T., & Mickle, M.H. (2008). Radio frequency identification prototyping. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 13(2), 1-22.Association for Computing Machinery (ACM). doi: 10.1145/1344418.1344425.

JONES, A.K., KERBYSON, D.J., RAJAMONY, R., & WEEMS, C. (2008). GUEST EDITOR'S NOTE: LARGE-SCALE PARALLEL PROCESSING. Parallel Processing Letters, 18(04), 449-451.World Scientific Publishing. doi: 10.1142/s0129626408003508.

Mickle, M.H., Cain, J.T., & Jones, A.K. (2008). Intellectual Property and Ubiquitous RFID. 1(1), 59-67.

Shao, S., Zhang, Y., Jones, A.K., & Melhem, R. (2008). Symbolic Expression Analysis for Compiled Communication* *This work is partially supported by NSF award number 0702452. 2008 IEEE International Symposium on Parallel and Distributed Processing, 18(4), 1-8.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2008.4536344.

Dontharaju, S., Tung, S., Jones, A.K., Mats, L., Panuski, J., Cain, J.T., & Mickle, M.H. (2007). The Unwinding of a Protocol. IEEE Applications and Practice, 1(1), 4-9.

Dontharaju, S., Tung, S., Jones, A.K., Mats, L., Panuski, J., Cain, J.T., & Mickle, M.H. (2007). THE UNWINDING OF A PROTOCOL. IEEE COMMUNICATIONS MAGAZINE, 45(4), 4-10.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/MCOM.2007.348669.

Dontharaju, S., Tung, S., Jones, A.K., Mats, L., Panuski, J., Cain, J.T., & Mickle, M.H. (2007). The unwinding of a protocol. IEEE Communications Magazine, 45(4), 4-10. doi: 10.1109/MCOM.2007.348669.

Jones, A.K., Hoare, R., Dontharaju, S., Tung, S., Sprang, R., Fazekas, J., Cain, J.T., & Mickle, M.H. (2007). An automated, FPGA-based reconfigurable, low-power RFID tag. MICROPROCESSORS AND MICROSYSTEMS, 31(2), 116-134.Elsevier. doi: 10.1016/j.micpro.2006.03.002.

Hawrylak, P.J., Mats, L., Cain, J.T., Jones, A.K., Tung, S., & Mickle, M.H. (2006). Ultra Low-power Computing Systems for Wireless Devices. International Review on Computers and Software (IRECOS), 1(1), 1-10.

Hoare, R.R., Ding, Z., & Jones, A.K. (2006). Interconnect routing and scheduling---A near-optimal real-time hardware scheduler for large cardinality crossbar switches. Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06, 68(11), 94-es.Association for Computing Machinery (ACM). doi: 10.1145/1188455.1188554.

Hoare, R.R., Jones, A.K., Kusic, D., Fazekas, J., Foster, J., Tung, S., & McCloud, M. (2006). Rapid VLIW processor customization for signal processing applications using combinational hardware functions. EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING, 2006(1), 046472.Springer Nature. doi: 10.1155/ASP/2006/46472.

Jones, A.K., Dontharaju, S., Tung, S., Hawrylak, P.J., Mats, L., Hoare, R., Cain, J.T., & Mickle, M.H. (2006). Passive active radio frequency identification tags. International Journal of Radio Frequency Identification Technology and Applications, 1(1), 52.Inderscience Publishers. doi: 10.1504/ijrfita.2006.010711.

Jones, A.K., Hoare, R., Kusic, D., Mehta, G., Fazekas, J., & Foster, J. (2006). Reducing power while increasing performance with supercisc. ACM Transactions on Embedded Computing Systems, 5(3), 658-686.Association for Computing Machinery (ACM). doi: 10.1145/1165780.1165785.

Jones, A.K., Hoare, R., Kusic, D., Stander, J., Mehta, G., & Fazekas, J. (2006). A VLIW processor with hardware functions: Increasing performance while reducing power. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 53(11), 1250-1254.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TCSII.2006.882849.

Jones, A.K., Zheng, J.A., & Amer, A. (2006). Entropy based evaluation of communication predictability in parallel applications. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, E89D(2), 469-478.Institute of Electronics, Information and Communications Engineers (IEICE). doi: 10.1093/ietisy/e89-d.2.469.

Lucas, J.M., Hoare, R., Kourtev, I.S., & Jones, A.K. (2006). Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). MICROPROCESSORS AND MICROSYSTEMS, 30(7), 445-456.Elsevier. doi: 10.1016/j.micpro.2006.04.002.

Mehta, G., Hoare, R.R., Stander, J., Lucas, J., Hunsaker, B., & Jones, A.K. (2006). A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. Journal of Low Power Electronics (JOLPE), 2(2), 148-164.

Hoare, R.R., Ding, Z., Tung, S., Melhem, R., & Jones, A.K. (2005). A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 65(10), 1237-1252.Elsevier. doi: 10.1016/j.jpdc.2005.04.022.

Tang, X., Jiang, T., Jones, A.K., & Banerjee, P. (2005). Behavioral Synthesis with power Estimation and Optimization for Unscheduled Data-Dominated Circuits. Journal of Low Power Electronics, 1(3), 259-272.

Jones, A., & Banerjee, P. (2003). An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs**This research was supported by DARPA under contract F33615-01-C-1631 and by NASA under contract 276685. 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003., 2003-January, 284-285.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/fpga.2003.1227272.

Jones, A., Bagchi, D., Pal, S., Tang, X., Choudhary, A., & Banerjee, P. (2002). PACT HDL. Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '02, 188-197.Association for Computing Machinery (ACM). doi: 10.1145/581630.581659.

Banerjee, P., Shenoy, N., Choudhary, A., Hauck, S., Bachmann, C., Haldar, M., Joisha, P., Jones, A., Kanhare, A., Nayak, A., Periyacheri, S., Walkden, M., & Zaretsky, D. (2000). A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems. 2014 IEEE 26th International Conference on Tools with Artificial Intelligence, 39-48.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/fpga.2000.903391.

Gupta, R.K., & Montgomery, S. (1975). STATUS OF LITHIUM PATIENTS AS BLOOD-DONORS. The Lancet, 305(7911), 860.Elsevier. doi: 10.1016/s0140-6736(75)93038-x.

Zhuang, J., Yang, Z., Ji, S., Huang, H., Jones, A.K., Hu, J., Shi, Y., & Zhou, P. (2024). SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. In Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, (pp. 55-66).Association for Computing Machinery (ACM). doi: 10.1145/3626202.3637569.

Zhou, P., Zhuang, J., Cahoon, S., Tang, Y., Yang, Z., Chen, X., Shi, Y., Hu, J., & Jones, A.K. (2023). REFRESH FPGAs: Sustainable FPGA Chiplet Architectures. In Proceedings of the 14th International Green and Sustainable Computing Conference, 20, (pp. 1-3).Association for Computing Machinery (ACM). doi: 10.1145/3634769.3634798.

Zhuang, J., Lau, J., Ye, H., Yang, Z., Du, Y., Lo, J., Denolf, K., Neuendorffer, S., Jones, A., Hu, J., Chen, D., Cong, J., & Zhou, P. (2023). CHARM: C omposing H eterogeneous A ccele R ators for M atrix Multiply on Versal ACAP Architecture. In Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, (pp. 153-164).Association for Computing Machinery (ACM). doi: 10.1145/3543622.3573210.

Jones, A.K., Longofono, S., Ollivier, S., Kline, D., Zhang, J., & Melhem, R. (2021). Tuning Memory Fault Tolerance on the Edge. In Proceedings of the 2021 Great Lakes Symposium on VLSI, (pp. 421-424).Association for Computing Machinery (ACM). doi: 10.1145/3453688.3462231.

Kline, D., Zhang, J., Melhem, R., & Jones, A.K. (2020). FLOWER and FaME: A Low Overhead Bit-level Fault-map and Fault-tolerance Approach for Deeply Scaled Memories. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 00, (pp. 356-368).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca47549.2020.00037.

Kline, D., Longofono, S., Melhem, R., & Jones, A.K. (2019). Predicting Single Event Effects in DRAM. In 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 00, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dft.2019.8875328.

Kline, D., Longofono, S., Ollivier, S., Higgins, E., Melhem, R., & Jones, A.K. (2019). PREMSim: A Resilience Framework for Modeling Traditional and Emerging Memory Reliability. In 2019 IEEE 27th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 00, (pp. 396-409).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mascots.2019.00049.

Longofono, S., Kline, D., Melhem, R., & Jones, A.K. (2019). Toward Secure, Reliable, and Energy Efficient Phase-change Main Memory with MACE. In 2019 Tenth International Green and Sustainable Computing Conference (IGSC), 00, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igsc48788.2019.8957202.

Ollivier, S., Kline, D., Kawsher, R., Melhem, R., Banja, S., & Jones, A.K. (2019). Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories. In 2019 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 00, (pp. 375-387).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dsn.2019.00047.

Ollivier, S., Kline, D., Kawsher, R., Melhem, R., Banja, S., & Jones, A.K. (2019). The Power of Orthogonality. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 00, (pp. 100-102).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isvlsi.2019.00026.

Brunvand, E., Kline, D., & Jones, A.K. (2018). Dark Silicon Considered Harmful: A Case for Truly Green Computing. In 2018 Ninth International Green and Sustainable Computing Conference (IGSC), 00, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2018.8752110.

Kline, D., & Jones, A.K. (2018). Achieving Secure, Reliable, and Sustainable Next Generation Computing Memories. In 2018 Ninth International Green and Sustainable Computing Conference (IGSC), 00, (pp. 1-2).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2018.8752128.

Seyedzadeh, S.M., Jones, A.K., & Melhem, R. (2018). Enabling Fine-Grain Restricted Coset Coding Through Word-Level Compression for PCM. In 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018-February, (pp. 350-361).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hpca.2018.00038.

Seyedzadeh, S.M., Jones, A.K., & Melhem, R. (2018). Mitigating Wordline Crosstalk Using Adaptive Trees of Counters. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), (pp. 612-623).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isca.2018.00057.

Seyedzadeh, S.M., Jones, A.K., & Melhem, R. (2018). Improving Sustainability Through Disturbance Crosstalk Mitigation in Deeply Scaled Phase-change Memory. In 2018 Ninth International Green and Sustainable Computing Conference (IGSC), 00, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2018.8752107.

Kline, D., Melhem, R., & Jones, A.K. (2017). Sustainable Fault Management and Error Correction for Next-Generation Main Memories. In 2017 Eighth International Green and Sustainable Computing Conference (IGSC), 2017-October, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2017.8323584.

Kline, D., Melhem, R., & Jones, A.K. (2017). Holistic Energy Efficient Crosstalk Mitigation in DRAM. In 2017 Eighth International Green and Sustainable Computing Conference (IGSC), 2017-October, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2017.8323590.

Kline, D., Parshook, N., Johnson, A., Stine, J.E., Stanchina, W., Brunvand, E., & Jones, A.K. (2017). Sustainable IC Design and Fabrication. In 2017 Eighth International Green and Sustainable Computing Conference (IGSC), 2017-October, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2017.8323572.

Seyedzadeh, S.M., Kline, D., Jones, A.K., & Melhem, R. (2017). Mitigating bitline crosstalk noise in DRAM memories. In Proceedings of the International Symposium on Memory Systems, Part F131197, (pp. 205-216).Association for Computing Machinery (ACM). doi: 10.1145/3132402.3132410.

Zhang, J., Kline, D., Fang, L., Melhem, R., & Jones, A.K. (2017). Yoda: Judge Me by My Size, do You? Dramatically Improving Error Mitigation Through Small Increases in Encoding Bits. In 2017 IEEE International Conference on Computer Design (ICCD), (pp. 395-398).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccd.2017.68.

Zhang, J., Kline, D., Fang, L., Melhem, R., & Jones, A.K. (2017). Dynamic Partitioning to Mitigate Stuck-At Faults in Emerging Memories. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017-November, (pp. 651-658).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2017.8203839.

Alkabani, Y., Koopmans, Z., Xu, H., Jones, A.K., & Melhem, R. (2016). Write Pulse Scaling for Energy Efficient STT-MRAM. In 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016-September, (pp. 248-253).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isvlsi.2016.118.

Bayram, I., Eken, E., Kline, D., Parshook, N., Chen, Y., & Jones, A.K. (2016). Modeling STT-RAM Fabrication Cost and Impacts in NVSim. In 2016 Seventh International Green and Sustainable Computing Conference (IGSC), (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2016.7892599.

Kline, D., Parshook, N., Get, X., Brunvand, E., Melhem, R., Chrysanthis, P.K., & Jones, A.K. (2016). Holistically Evaluating the Environmental Impacts in Modern Computing Systems. In 2016 Seventh International Green and Sustainable Computing Conference (IGSC), (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2016.7892605.

Seyedzadeh, S.M., Maddah, R., Jones, A., & Melhem, R. (2016). Leveraging ECC to Mitigate Read Disturbance, False Reads and Write Faults in STT-RAM. In 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), (pp. 215-226).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/dsn.2016.28.

Jones, A.K., Li, H., Coskun, A.K., & Margala, M. (2015). Foreword. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 20-22-May-2015, (pp. iii-iv).

Xu, H., Bilec, M.M., Collinge, W.O., Schaefer, L.A., Landis, A.E., & Jones, A.K. (2015). Lynx: A Self-Organizing Wireless Sensor Network with Commodity Palmtop Computers. In 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2015-July, (pp. 1-7).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/slip.2015.7171712.

Xu, H., Li, Y., Collinge, W.O., Schaefer, L.A., Bilec, M.M., Jones, A.K., & Landis, A.E. (2015). Improving Efficiency of Wireless Sensor Networks Through Lightweight In-Memory Compression. In 2015 Sixth International Green and Sustainable Computing Conference (IGSC), (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2015.7393696.

Sun, Z., Bi, X., Jones, A.K., & Li, H. (2014). Design exploration of racetrack lower-level caches. In Proceedings of the 2014 international symposium on Low power electronics and design, 2015-October, (pp. 263-266).Association for Computing Machinery (ACM). doi: 10.1145/2627369.2627651.

Jones, A.K., Chen, Y., Collinge, W.O., Xu, H., Schaefer, L.A., Landis, A.E., & Bilec, M.M. (2013). Considering Fabrication in Sustainable Computing. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 206-210).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/iccad.2013.6691120.

Jones, A.K., Liao, L., Collinge, W.O., Xu, H., Schaefer, L.A., Landis, A.E., & Bilec, M.M. (2013). Green Computing: A Life Cycle Perspective. In 2013 International Green Computing Conference Proceedings, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2013.6604497.

Li, Y., Zhang, Y., Li, H., Chen, Y., & Jones, A.K. (2013). C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache. In ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(4), (p. 52).Association for Computing Machinery (ACM). doi: 10.1145/2555289.2555308.

Mao, M., Li, H., Jones, A.K., & Chen, Y. (2013). Coordinating prefetching and STT-RAM based last-level cache management for multicore systems. In Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI, (pp. 55-60).Association for Computing Machinery (ACM). doi: 10.1145/2483028.2483060.

Xu, H., Bilec, M.M., Schaefer, L.A., Landis, A.E., & Jones, A.K. (2013). Ocelot: A Wireless Sensor Network and Computing Engine with Commodity Palmtop Computers. In 2013 International Green Computing Conference Proceedings, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/igcc.2013.6604482.

Abousamra, A.K., Melhem, R.G., & Jones, A.K. (2012). DéjàVu Switching for Multiplane NoCs. In 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, (pp. 11-18).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/nocs.2012.9.

Collinge, W.O., Landis, A.E., Jones, A.K., Schaefer, L.A., & Bilec, M.M. (2012). Integrating Indoor Environmental Quality Metrics in a Dynamic Life Cycle Assessment Framework For Buildings. In 2012 IEEE International Symposium on Sustainable Systems and Technology (ISSST), 1, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/issst.2012.6227992.

Li, Y., & Jones, A.K. (2012). Cross-layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics. In 2012 IEEE Computer Society Annual Symposium on VLSI, 1, (pp. 404-409).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isvlsi.2012.65.

Li, Y., Chen, Y., & Jones, A.K. (2012). A software approach for combating asymmetries of non-volatile memories. In Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, (pp. 191-196).Association for Computing Machinery (ACM). doi: 10.1145/2333660.2333708.

Li, Y., Melhem, R., & Jones, A.K. (2012). Practically private. In Proceedings of the 21st international conference on Parallel architectures and compilation techniques, (pp. 231-240).Association for Computing Machinery (ACM). doi: 10.1145/2370816.2370852.

Saunders, C.L., Landis, A.E., Jones, A.K., Schaefer, L.A., & Bilec, M.M. (2012). Utilizing Measured Energy Usage to Analyze Design Phase Energy Models. In 2012 IEEE International Symposium on Sustainable Systems and Technology (ISSST), 1, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/issst.2012.6227982.

Zhang, Y., Wang, X., Li, Y., Jones, A.K., & Chen, Y. (2012). Asymmetry of MTJ switching and its implication to STT-RAM designs. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1313-1318).

Abousamra, A., Melhem, R., & Jones, A. (2011). Two-hop free-space based optical interconnects for chip multiprocessors. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, (pp. 89-96).Association for Computing Machinery (ACM). doi: 10.1145/1999946.1999961.

Abousamra, A.K., Jones, A.K., & Melhem, R.G. (2011). NoC-aware cache design for multithreaded execution on tiled chip multiprocessors. In Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, (pp. 197-205).Association for Computing Machinery (ACM). doi: 10.1145/1944862.1944891.

Collinge, W.O., Liao, L., Xu, H., Saunders, C.L., Bilec, M.M., Landis, A.E., Jones, A.K., & Schaefer, L.A. (2011). Enabling Dynamic Life Cycle Assessment of Buildings with Wireless Sensor Networks. In Proceedings of the 2011 IEEE International Symposium on Sustainable Systems and Technology, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/issst.2011.5936846.

Xu, H., Eronini, I.U., Mao, Z.H., & Jones, A.K. (2011). Towards Improving Renewable Resource Utilization with Plug-in Electric Vehicles. In ISGT 2011, 1, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isgt.2011.5759189.

Abousamra, A.K., Melhem, R.G., & Jones, A.K. (2010). NoC-aware cache design for chip multiprocessors. In Proceedings of the 19th international conference on Parallel architectures and compilation techniques, (pp. 565-566).Association for Computing Machinery (ACM). doi: 10.1145/1854273.1854354.

Ihrig, C.J., Melhem, R., & Jones, A.K. (2010). Automated modeling and emulation of interconnect designs for many-core chip multiprocessors. In Proceedings of the 47th Design Automation Conference, (pp. 431-436).Association for Computing Machinery (ACM). doi: 10.1145/1837274.1837383.

Li, Y., Abousamra, A., Melhem, R., & Jones, A.K. (2010). Compiler-assisted data distribution for chip multiprocessors. In Proceedings of the 19th international conference on Parallel architectures and compilation techniques, (pp. 501-512).Association for Computing Machinery (ACM). doi: 10.1145/1854273.1854335.

Li, Y., Melhem, R., & Jones, A.K. (2010). Compiler-based data classification for hybrid caching. In Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture, (pp. 1-7).Association for Computing Machinery (ACM). doi: 10.1145/1739025.1739030.

O'Connor, R., Reed, G., Mao, Z.H., & Jones, A.K. (2010). Improving Renewable Resource Utilization through Integrated Generation Management. In IEEE PES General Meeting, (pp. 1-6).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/pes.2010.5589530.

Reed, G.F., Grainger, B.M., Bassi, H., Taylor, E., Mao, Z.H., & Jones, A.K. (2010). Analysis of High Capacity Power Electronic Technologies for Integration of Green Energy Management. In IEEE PES T&D 2010, (pp. 1-10).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tdc.2010.5484374.

Wang, H., Xu, H., & Jones, A.K. (2010). Crucial Issues in Logistic Planning for Electric Vehicle Battery Application Service. In 2010 International Conference on Optoelectronics and Image Processing, 1, (pp. 362-366).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icoip.2010.125.

Abousamra, A., Melhem, R., & Jones, A. (2009). Winning with Pinning in NoC. In 2009 17th IEEE Symposium on High Performance Interconnects, (pp. 13-21).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/hoti.2009.15.

Ihrig, C.J., Dhanabalan, G.J., & Jones, A.K. (2009). A low-power CMOS thyristor based delay element with programmability extensions. In Proceedings of the 19th ACM Great Lakes symposium on VLSI, (pp. 297-302).Association for Computing Machinery (ACM). doi: 10.1145/1531542.1531611.

Rucinski, A. (2009). Message from the General Chair. In 2009 IEEE International Conference on Microelectronic Systems Education, (pp. 1-2).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mse.2009.5270850.

JONES, A.K., SHAO, S., ZHANG, Y., & MELHEM, R. (2008). SYMBOLIC EXPRESSION ANALYSIS FOR COMPILED COMMUNICATION. In Parallel Processing Letters, 18(04), (pp. 567-587).World Scientific Publishing. doi: 10.1142/s0129626408003570.

Mehta, G., Ihrig, C.J., & Jones, A.K. (2008). Reducing Energy by Exploring Heterogeneity in a Coarse-grain Fabric * *This work was partially supported by The Technology Collaborative. In 2008 IEEE International Symposium on Parallel and Distributed Processing, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2008.4536532.

Tung, S., & Jones, A.K. (2008). Physical Layer Design Automation for RFID Systems. In 2008 IEEE International Symposium on Parallel and Distributed Processing, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2008.4536530.

Yu, Y., Hoare, R.R., & Jones, A.K. (2008). A CAM-based Intrusion Detection System for Single-packet Attack Detection* *This work was supported in part by The Technology Collaborative. In 2008 IEEE International Symposium on Parallel and Distributed Processing, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2008.4536531.

Ihrig, C.J., Stander, J., & Jones, A.K. (2007). Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions. In 2007 IEEE International Parallel and Distributed Processing Symposium, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2007.370468.

Jones, A.K., Dontharaju, S.R., Mats, L., Cain, J.T., & Mickle, M.H. (2007). Exploring RFID Prototyping in the Virtual Laboratory. In 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), (pp. 137-138).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mse.2007.41.

Jones, A.K., Hoare, R.R., St Onge, J., Lucas, J., Shao, S., & Melhem, R. (2007). Linking Compilation and Visualization for Massively Parallel Programs* *This work is in the context of the PERCS project at IBM, which is supported in part by the Defense Advanced Research Projects Agency (DARPA) under contract No. NBCH3039004. In 2007 IEEE International Parallel and Distributed Processing Symposium, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2007.370470.

Jones, A.K., Levitan, S., Rutenbar, R.A., & Xie, Y. (2007). Collaborative VLSI-CAD Instruction in the Digital Sandbox** These collaborative course initiatives were supported by The Technology Collaborative. In 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07), (pp. 141-142).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/mse.2007.29.

Mehta, G., Stander, J., Baz, M., Hunsaker, B., & Jones, A.K. (2007). Interconnect Customization for a Coarse-grained Reconfigurable Fabric. In 2008 IEEE International Symposium on Parallel and Distributed Processing, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2007.370370.

Ding, Z., Hoare, R.R., Jones, A.K., & Melhem, R. (2006). Interconnect routing and scheduling---Level-wise scheduling algorithm for fat tree interconnection networks. In Proceedings of the 2006 ACM/IEEE conference on Supercomputing - SC '06, (pp. 96-es).Association for Computing Machinery (ACM). doi: 10.1145/1188455.1188556.

Jones, A.K., Hoare, R.R., Dontharaju, S.R., Tung, S., Sprang, R., Fazekas, J., Cain, J.T., & Mickle, M.H. (2006). A Field Programmable RFID Tag and Associated Design Flow. In 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, (pp. 165-174).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/fccm.2006.7.

Jones, A.K., Hoare, R.R., Dontharaju, S.R., Tung, S., Sprang, R., Fazekas, J., Cain, J.T., & Mickle, M.H. (2006). An automated, reconfigurable, low-power RFID tag. In Proceedings of the 43rd annual conference on Design automation - DAC '06, (pp. 131-136).Association for Computing Machinery (ACM). doi: 10.1145/1146909.1146948.

Jones, A.K., Kourtev, I.S., Hoare, R., Lucas, J.M.Jones, A.K., Kourtev, I.S., Hoare, R., Lucas, J.M. (2006). Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). In 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, (pp. 299-300).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/fccm.2006.68.

Mehta, G., Hoare, R.R., Stander, J., & Jones, A.K. (2006). A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. In 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, (pp. 309-310).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/fccm.2006.9.

Mehta, G., Hoare, R.R., Stander, J., & Jones, A.K. (2006). Design Space Exploration for Low-Power Reconfigurable Fabrics. In Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006, (pp. 1-4).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2006.1639484.

Shao, S., Jones, A.K., & Melhem, R. (2006). A Cornpilor-basod Comrnunication Analysis Approach for Multiprocessor Systems**This work is in the context of the PERCS project at IBM which is supported in part by the Defence Advanced Research Projects Agency(DARPA) under Contract No. NBCH3039004. In Proceedings 20th IEEE International Parallel & Distributed Processing Symposium, 2006, (pp. 1-10).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2006.1639322.

Yu, Y., Hoare, R.R., Jones, A.K., & Sprang, R. (2006). A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. In Proceedings - IEEE International Symposium on Circuits and Systems, (pp. 791-794).

Barker, K.J., Benner, A., Hoare, R., Hoisie, A., Jones, A.K., Kerbyson, D.K., Li, D., Melhem, R., Rajamony, R., Schenfeld, E., Shao, S., Stunkel, C., & Walker, P. (2005). On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. In ACM/IEEE SC 2005 Conference (SC'05), 2005-November, (p. 16).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/sc.2005.48.

Ding, Z., Hoare, R., Jones, A., Li, D., Shao, S., Tung, S., Zheng, J., & Melhem, R. (2005). Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. In 19th IEEE International Parallel and Distributed Processing Symposium, 2005, (pp. 1-10).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2005.416.

Jones, A.K., Hoare, R., Kusic, D., Fazekas, J., & Foster, J. (2005). An FPGA-based VLIW processor with custom hardware execution. In Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, (pp. 107-117).Association for Computing Machinery (ACM). doi: 10.1145/1046192.1046207.

Kusic, D., Hoare, R., Jones, A.K., Fazekas, J., & Foster, J. (2005). Extracting Speedup from C-Code With Poor Instruction-Level Parallelism. In 19th IEEE International Parallel and Distributed Processing Symposium, 2005, (pp. 1-8).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/ipdps.2005.216.

Lucas, J.M., Hoare, R., & Jones, A.K. (2005). Optimizing Technology Mapping for FPGAs using CAMs. In 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), 2005, (pp. 293-294).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/fccm.2005.50.

Tang, X., Jiang, T., Jones, A., & Banerjee, P. (2005). Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation**This work was supported by DARPA under contract no F33615-0 1-C-1631. In 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, (pp. 267-273).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/icvd.2005.62.

Brady, B.A., Jones, A.K., & Kourtev, I.S. (2004). Efficient CAD development for emerging technologies using Objective-C and Cocoa. In 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, (pp. 369-372).

Jones, A., Tang, X., & Banerjee, P. (2004). Compile-time simulation for low-power optimization using SystemC. In Proceedings of the IASTED International Conference on Modeling and Simulation, (pp. 78-83).

Jones, A.K., Hoare, R., Kourtev, I.S., Fazekas, J., Kusic, D., Foster, J., Boddie, S., & Muaydh, A. (2004). A 64-way VLIW/SIMD FPGA architecture and design flow. In 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, (pp. 499-502).

Lucas, J.M., Hoare, R., Kourtev, I.S., & Jones, A.K. (2004). LURU: Global-scope FPGA technology mapping with Content-Addressable Memories. In 11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004, (pp. 599-602).

Mukherjee, R., Jones, A., & Banerjee, P. (2004). Handling Data Streams while Compiling C Programs onto Hardware. In IEEE Computer Society Annual Symposium on VLSI, (pp. 271-272).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/isvlsi.2004.1339553.

Jiang, T., Tang, X., Jones, A., & Banerjee, P. (2003). Optimizing Power While Exploiting Fine Grain Parallelism on FPGAs. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, 15(1), (pp. 357-362).

Mukherjee, R., Jones, A., & Banerjee, P. (2003). System level synthesis of multiple ip blocks in the behavioral synthesis tool. In Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, 15(1), (pp. 363-368).

Tang, X., Jiang, T., Jones, A., & Banerjee, P. (2003). Compiler Optimizations in the PACT HDL Behavioral Synthesis Tool for ASICs and FPGAs $\ast$. In IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings., (pp. 189-192).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/soc.2003.1241490.