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Hai Li

Associate Professor
Dr. Li's Site: Evolutionary Intelligence Lab Electrical and Computer Engineering

about

(2013) Best Paper Nomination, International Conference on Computer Aided Desing (ICCAD) for the paper titled "Unleashing the POtential of MLC STT-RAM Caches".

(2013) Air Force Visiting Faculty Research Program (VFRP) Fellowship, AFRL/RIB, Rome, NY.

(2013) DARPA Young Faculty Award (YFA).

(2013) Best Paper Award, Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI (GLSVLSI) for the paper titled "Coordinating Prefetching and STT-RAM based Last-level Cache Management for Multicore Systems.

(2012) WICAT Center and NYU WIRELESS Research Distribution Award.

(2012) NSF Career Program.

(2012) Best Paper Nomination, International Conference on Computer Aided Design (ICCAD) for the paper titled "Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches,".

(2011) Air Force Summer Faculty Fellowship Program Award (AF-SFFP), AFRL/RITC, Rome, NY, summer 2011. (Ranking 2 of 300+ applicants) (F49620-02-C-0015).

(2011) Best Paper Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper titled "Geometry Variations Analysis of TiO2 Thin Film and Spintronic Memristors".

(2010) Best Paper Nomination, Design, Automation & Test in Europe Conference and Exhibition (DATE) for the paper titled "A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM),".

(2010) Best Paper Nomination, the 11th International Symposium on Quality Electronic Design (ISQED) for the paper titled "Scalability of PCMO-based Resistive Switch Device in DSM Technologies.

(2010) Best Paper Award, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) for the paper titled "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM".

(2008) Best Paper Award, the 9th International Symposium on Quality Electronic Design (ISQED) for paper titled "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)".

(2007) Intel Penryn Project Award for contribution on power reduction methodology, Microprocessor Product Group, Intel Corporation.

(2005) Qualstar Award for 65nm unified design methodology, Qualcomm CDMA Technology, Qualcomm Inc..

PhD, Electrical and Computer Engineering, Purdue University, 2004

MS, Microelectronics, Tsinghua University, 2000

BS, Electronic Engineering, Tsinghua University, 1998

Zhang, Y., Wen, W., Li, H., & Chen, Y. (2017). Metallic Spintronic Devices. In Metallic Spintronic Devices. (pp. 71-103).CRC Press. doi: 10.1201/b17238.

Sun, Z., Bi, X., Wu, W., Yoo, S., & Li, H.H. (2016). Array Organization and Data Management Exploration in Racetrack Memory. IEEE TRANSACTIONS ON COMPUTERS, 65(4), 1041-1054.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TC.2014.2360545.

Yang, J., Sun, Z., Wang, X., Chen, Y., & Li, H. (2016). Spintronic Memristor as Interface Between DNA and Solid State Devices. 6, (pp. 212-221).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JETCAS.2016.2547700.

Dong, Z., Duan, S., Hu, X., Wang, L., & Li, H. (2014). A Novel Memristive Multilayer Feedforward Small-World Neural Network with Its Applications in PID Control. SCIENTIFIC WORLD JOURNAL, 2014(384828), 394828.Hindawi Limited. doi: 10.1155/2014/394828.

Hu, M., Li, H., Chen, Y., Wu, Q., Rose, G.S., & Linderman, R.W. (2014). Memristor Crossbar-Based Neuromorphic Computing System: A Case Study. IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 25(10), 1864-1878.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TNNLS.2013.2296777.

Li, H., Sun, Z., Bi, X., Wong, W.F., Zhu, X., & Wu, W. (2014). STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices. In Emerging Memory Technologies. 9781441995513, (pp. 169-199).Springer New York. doi: 10.1007/978-1-4419-9551-3_7.

Sun, Z., Bi, X., Li, H.H., Wong, W.F., & Zhu, X. (2014). STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 22(6), 1281-1293.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2013.2267754.

Li, Y., Zhang, Y., Li, H., Chen, Y., & Jones, A. (2013). C1C: A Configurable, Compiler-guided STT-RAM L1 Cache. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) and ACM Transactions on Architecture and Code Optimization (TACO), 110(4), 52.

Miao Hu, Hai Li, Yiran Chen, Qing Wu, & Rose, G.S. (2013). BSB training scheme implementation on memristor-based circuit. 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications (CISDA), (pp. 80-87).IEEE. doi: 10.1109/cisda.2013.6595431.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2013). Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices. ACM Transactions on Design Automation of Electronic Systems (TODAES), 8(4), 57.

Bi, X., Li, H., & Wang, X. (2012). STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence. IEEE Transactions on Magnetics (TMAG), 48(11), 3821-3824.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., & Zhang, T. (2012). A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 47(2), 560-573.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/JSSC.2011.2170778.

LI, H.H., & SUN, Z. (2012). VOLTAGE DRIVEN NONDESTRUCTIVE SELF-REFERENCE SENSING FOR STT-RAM YIELD ENHANCEMENT. SPIN, 02(03), 1240008.World Scientific Pub Co Pte Lt. doi: 10.1142/s2010324712400085.

Sun, Z., Chen, X., Zhang, Y., Li, H., & Chen, Y. (2012). Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 8(2), 1-16.Association for Computing Machinery (ACM). doi: 10.1145/2180878.2180885.

Sun, Z., Li, H., Chen, Y., & Wang, X. (2012). Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 20(11), 2020-2030.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TVLSI.2011.2166282.

Sun, Z., Li, H., Wang, X., & Chen, Y. (2012). MTJ Design Margin Exploration for Self-Reference Sensing. Journal of Applied Physics (JAP), 111, 07C726.

Chen, Y., Wong, W.F., Li, H., & Koh, C.K. (2011). Processor caches built using multi-level spin-transfer torque RAM cells. IEEE/ACM International Symposium on Low Power Electronics and Design, 73-78.IEEE. doi: 10.1109/islped.2011.5993610.

Dong, X., Wu, X., Xie, Y., Chen, Y., & Li, H. (2011). Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. IET COMPUTERS AND DIGITAL TECHNIQUES, 5(3), 213-220.Institution of Engineering and Technology (IET). doi: 10.1049/iet-cdt.2009.0091.

Hu, M., Li, H.H., Chen, Y., & Wang, X. (2011). Spintronic Memristor: Compact Model and Statistical Analysis. Journal of Low Power Electronics, 7(2), 234-244.American Scientific Publishers. doi: 10.1166/jolpe.2011.1131.

Li, H., Wang, X., Ong, Z.L., Wong, W.F., Zhang, Y., Wang, P., & Chen, Y. (2011). Performance, Power, and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-Level Requirement. IEEE TRANSACTIONS ON MAGNETICS, 47(10), 2356-2359.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2011.2159262.

Wang, P., Wang, X., Zhang, Y., Li, H., Levitan, S.P., & Chen, Y. (2011). Nonpersistent Errors Optimization in Spin-MOS Logic and Storage Circuitry. IEEE TRANSACTIONS ON MAGNETICS, 47(10), 3860-3863.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2011.2153838.

Zhang, Y., Wang, X., Li, H., & Chen, Y. (2011). STT-RAM Cell Optimization Considering MTJ and CMOS Variations. IEEE TRANSACTIONS ON MAGNETICS, 47(10), 2962-2965.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2011.2158810.

Zhu, W., Li, H., Chen, Y., & Wang, X. (2011). Current Switching in MgO-Based Magnetic Tunneling Junctions. IEEE TRANSACTIONS ON MAGNETICS, 47(1), 156-160.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/TMAG.2010.2085441.

Chen, Y., & Li, H. (2010). Patents Relevant to Cross-Point Memory Array. Recent Patents on Electrical Engineeringe, 3(2), 114-124.Bentham Science Publishers Ltd. doi: 10.2174/1874476111003020114.

Chen, Y., Li, H., Chen, C.K., Roy, K., Li, J., & Sun, G. (2010). Variable-Latency Adder (VL-Adder): New Arithmetic Circuit Design Practice for Low Power and NBTI Tolerance. IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 18(11), 1621-1624.

Chen, Y., Wang, X., Li, H., Xi, H., Yan, Y., & Zhu, W. (2010). Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(12), 1724-1734.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2009.2032192.

Xi, H., Stricklin, J., Li, H., Chen, Y., Wang, X., Zheng, Y., Gao, Z., & Tang, M.X. (2010). Spin Transfer Torque Memory with Thermal Assist Mechanism: A Case Study. IEEE Transaction on Magnetics (TMAG), 46(3), 860-865.

Xiaobin Wang, Yiran Chen, Ying Gu, & Hai Li. (2010). Spintronic Memristor Temperature Sensor. IEEE Electron Device Letters, 31(1), 20-22.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/led.2009.2035643.

Yiran Chen, Wei Tian, Hai Li, Xiaobin Wang, & Wenzhong Zhu. (2010). PCMO Device With High Switching Stability. IEEE Electron Device Letters, 31(8), 866-868.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/led.2010.2050457.

Koh, C.K., Wong, W.F., Chen, Y., & Li, H. (2009). Tolerating Process Variations in Large, Set Associative Caches: The Buddy Cache. ACM Transactions on Architecture and Code Optimization (TACO), 6(8), 34 pages.

Xiaobin Wang, Yiran Chen, Haiwen Xi, Hai Li, & Dimitrov, D. (2009). Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion. IEEE Electron Device Letters, 30(3), 294-297.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/led.2008.2012270.

Yiran Chen, Hai Li, Roy, K., & Cheng-Kok Koh. (2009). Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(12), 1749-1752.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2008.2007843.

Wang, X., Chen, Y., Li, H., Liu, H., & Dimitrov, D. (2008). Spin Torque Random Access Memory down to 22nm Technology. IEEE Transaction on Magnetics (TMAG), 44(11), 2479-2482.

Xiaobin Wang, Yiran Chen, Hai Li, Dimitrov, D., & Liu, H. (2008). Spin Torque Random Access Memory Down to 22 nm Technology. In GD-03. IEEE Transactions on Magnetics, 44, (pp. 2479-2482).Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tmag.2008.2002386.

Li, H., Cher, C.Y., Vijaykumar, T.N., & Roy, K. (2005). Combined Circuit and Architectural Level Variable Supply-Voltage Scaling for Low Power. IEEE Trans. on Very Large Scale Integration (TVLSI) Systems, 13(5), 564-576.

Hai Li, Bhunia, S., Yiran Chen, Roy, K., & Vijaykumar, T.N. (2004). DCG: deterministic clock-gating for low-power microprocessor design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(3), 245-254.Institute of Electrical and Electronics Engineers (IEEE). doi: 10.1109/tvlsi.2004.824307.

Agarwal, H., Li, H., & Roy, K. (2003). A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron. IEEE Journal of Solid-State Circuits (JSSC), 38(2), 319-328.

Li, H., Wang, J., & Liu, Z. (2000). An Optimal Strategy for Parameter Extraction of BSIM3V3 Model. Microelectronics (in Chinese), 30(6), 387-390.

Li, Z., Liu, C., Li, H., & Chen, Y. (2017). Neuromorphic Hardware Acceleration Enabled by Emerging Technologies. International Symposium on Integrated Circuits (ISIC).Singapore. doi: 10.1007/978-3-319-54840-1_10.

Li, H.H., Hu, M., & Liu, B. (2016). Memristor modeling - static, statistical, and stochastic methodologies. IEEE Computer Society Annual Symposium on VLSI (ISVLSI).Tampa, Florida, USA. doi: 10.1049/pbcs029e_ch11.

Chao Zhang, Guangyu Sun, Weiqi Zhang, Fan Mi, Hai Li, & Zhao, W. (2015). Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. In The 20th Asia and South Pacific Design Automation Conference, (pp. 100-105).IEEE. doi: 10.1109/aspdac.2015.7058988.

Jones, A.K., Li, H., Coskun, A.K., & Margala, M. (2015). Foreword. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 20-22-May-2015, (pp. iii-iv).

Liang, H., Chen, Y.C., Luo, T., Zhang, W., Li, H., & He, B. (2015). Hierarchical Library Based Power Estimator for Versatile FPGAs. In 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, (pp. 25-32).IEEE. doi: 10.1109/mcsoc.2015.44.

Cavallaro, J.R., Zhang, T., Jones, A.K., & Li, H. (2014). GLSVLSI'14 chairs' welcome. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI.

Chen, L., Li, C., Huang, T., He, X., Li, H., & Chen, Y. (2014). STDP learning rule based on memristor with STDP property. In 2014 International Joint Conference on Neural Networks (IJCNN), (pp. 1-6).IEEE. doi: 10.1109/ijcnn.2014.6889506.

Eken, E., Zhang, Y., Wen, W., Joshi, R., Li, H., & Chen, Y. (2014). A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. In Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14.ACM Press. doi: 10.1145/2593069.2593075.

Hu, M., Wang, Y., Qiu, Q., Chen, Y., & Li, H. (2014). The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 831-836).IEEE. doi: 10.1109/aspdac.2014.6742993.

Hu, X., Feng, G., Li, H., Chen, Y., & Duan, S. (2014). An adjustable memristor model and its application in small-world neural networks. In 2014 International Joint Conference on Neural Networks (IJCNN), (pp. 7-14).IEEE. doi: 10.1109/ijcnn.2014.6889605.

Li, B., Wang, Y., Chen, Y., Li, H.H., & Yang, H. (2014). ICE: Inline calibration for memristor crossbar-based computing engine. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014.IEEE Conference Publications. doi: 10.7873/date2014.197.

Li, H., Hu, M., Li, C., & Duan, S. (2014). Memristor Modeling -- Static, Statistical, and Stochastic Methodologies. In 2014 IEEE Computer Society Annual Symposium on VLSI, (pp. 406-411).IEEE. doi: 10.1109/isvlsi.2014.108.

Li, H., Hu, M., Liu, X., Mao, M., Li, C., & Duan, S. (2014). Emerging memristor technology enabled next generation cortical processor. In 2014 27th IEEE International System-on-Chip Conference (SOCC), (pp. 377-382).IEEE. doi: 10.1109/socc.2014.6948958.

Li, H., Liu, X., Mao, M., Chen, Y., Wu, Q., & Bamell, M. (2014). Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). In 2014 International Symposium on Integrated Circuits (ISIC), (pp. 124-127).IEEE. doi: 10.1109/isicir.2014.7029530.

Liu, B., Li, H., Chen, Y., Li, X., Huang, T., Wu, Q., & Barnell, M. (2014). Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems. In 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015-January(January), (pp. 63-70).IEEE. doi: 10.1109/iccad.2014.7001330.

Liu, C., & Li, H. (2014). A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory Array. In 2014 IEEE Computer Society Annual Symposium on VLSI, (pp. 65-70).IEEE. doi: 10.1109/isvlsi.2014.32.

Mao, M., Wen, W., Zhang, Y., Chen, Y., & Li, H.H. (2014). Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. In Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, (pp. 1-6).ACM Press. doi: 10.1145/2593069.2593137.

Park, E., Yoo, S., Lee, S., & Li, H. (2014). Accelerating graph computation with racetrack memory and pointer-assisted graph representation. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, (pp. 1-4).IEEE Conference Publications. doi: 10.7873/date2014.172.

Sun, Z., Bi, X., Jones, A.K., & Li, H. (2014). Design exploration of racetrack lower-level caches. In Proceedings of the 2014 international symposium on Low power electronics and design, 2015-October, (pp. 263-266).ACM. doi: 10.1145/2627369.2627651.

Tang, T., Luo, R., Li, B., Li, H., Wang, Y., & Yang, H. (2014). Energy efficient spiking neural network design with RRAM devices. In 2014 International Symposium on Integrated Circuits (ISIC), (pp. 268-271).IEEE. doi: 10.1109/isicir.2014.7029565.

Wang, J., Roy, P., Wong, W.F., Bi, X., & Li, H. (2014). Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration. In 2014 IEEE 32nd International Conference on Computer Design (ICCD), (pp. 133-138).IEEE. doi: 10.1109/iccd.2014.6974672.

Wang, J., Tim, Y., Wong, W.F., Ong, Z.L., Sun, Z., & Li, H.H. (2014). A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), (pp. 610-615).IEEE. doi: 10.1109/aspdac.2014.6742958.

Wu, Q., Liu, B., Chen, Y., Li, H., Chen, Q., & Qiu, Q. (2014). Bio-inspired computing with resistive memories — models, architectures and applications. In 2014 IEEE International Symposium on Circuits and Systems (ISCAS), (pp. 834-837).IEEE. doi: 10.1109/iscas.2014.6865265.

Xiaoxiao Liu, Mengjie Mao, Hai Li, Yiran Chen, Hao Jiang, Yang, J.J., Qing Wu, & Barnell, M. (2014). A heterogeneous computing system with memristor-based neuromorphic accelerators. In 2014 IEEE High Performance Extreme Computing Conference (HPEC).IEEE. doi: 10.1109/hpec.2014.7040986.

Bi, X., Mao, M., Wang, D., & Li, H. (2013). Unleashing the potential of MLC STT-RAM caches. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 429-436).IEEE. doi: 10.1109/iccad.2013.6691153.

Bi, X., Weldon, M.A., & Li, H. (2013). STT-RAM Designs Supporting Dual-Port Accesses. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, (pp. 853-858).IEEE Conference Publications. doi: 10.7873/date.2013.180.

Chen, Y.C., Zhang, W., & Li, H.H. (2013). A hardware security scheme for RRAM-based FPGA. In 2013 23rd International Conference on Field programmable Logic and Applications, (pp. 1-4).IEEE. doi: 10.1109/fpl.2013.6645556.

Li, Y., Zhang, Y., Li, H., Chen, Y., & Jones, A.K. (2013). C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache. In ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 10(4). doi: 10.1145/2555289.2555308.

Liu, B., Hu, M., Li, H., Mao, Z.H., Chen, Y., Huang, T., & Zhang, W. (2013). Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine. In Proceedings of the 50th Annual Design Automation Conference on - DAC '13.ACM Press. doi: 10.1145/2463209.2488741.

Sun, Z., Wu, W., & Li, H.H. (2013). Cross-layer racetrack memory design for ultra high density and low power consumption. In Proceedings of the 50th Annual Design Automation Conference on - DAC '13.ACM Press. doi: 10.1145/2463209.2488799.

Wang, J., Tim, Y., Wong, W.F., & Li, H.H. (2013). A practical low-power memristor-based analog neural branch predictor. In International Symposium on Low Power Electronics and Design (ISLPED), (pp. 175-180).IEEE. doi: 10.1109/islped.2013.6629290.

Zhang, Y., Bayram, I., Wang, Y., Li, H., & Chen, Y. (2013). ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications. In 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 9-16).IEEE. doi: 10.1109/iccad.2013.6691091.

Bi, X., Zhang, C., Li, H., Chen, Y., & Pino, R.E. (2012). Spintronic memristor based temperature sensor design with CMOS current reference. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1301-1306).

Hu, M., Li, H., Wu, Q., Rose, G.S., & Chen, Y. (2012). Memristor crossbar based hardware realization of BSB recall function. In The 2012 International Joint Conference on Neural Networks (IJCNN), (pp. 1-7).IEEE. doi: 10.1109/ijcnn.2012.6252563.

Pino, R.E., Li, H.H., Chen, Y., Hu, M., & Liu, B. (2012). Statistical memristor modeling and case study in neuromorphic computing. In Proceedings of the 49th Annual Design Automation Conference on - DAC '12, (pp. 585-590).ACM Press. doi: 10.1145/2228360.2228466.

Xiang Chen, Jian Zeng, Yiran Chen, Wei Zhang, & Hai Li. (2012). Fine-grained dynamic voltage scaling on OLED display. In 17th Asia and South Pacific Design Automation Conference, (pp. 807-812).IEEE. doi: 10.1109/aspdac.2012.6165066.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., & Li, H. (2012). Architecting a common-source-line array for bipolar non-volatile memory devices. In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 1451-1454).

Chen, Y., & Li, H. (2011). Emerging sensing techniques for emerging memories. In 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), (pp. 204-210).IEEE. doi: 10.1109/aspdac.2011.5722185.

Joshi, R., Kanj, R., Peiyuan Wang, & Hai Li. (2011). Universal statistical cure for predicting memory loss. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 236-239).IEEE. doi: 10.1109/iccad.2011.6105333.

Wang, P., Chen, X., Chen, Y., Li, H., Kang, S., Zhu, X., & Wu, W. (2011). A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis. In 2011 IEEE Custom Integrated Circuits Conference (CICC), (pp. 1-4).IEEE. doi: 10.1109/cicc.2011.6055392.

Xue, C.J., Zhang, Y., Chen, Y., Sun, G., Yang, J.J., & Li, H. (2011). Emerging non-volatile memories. In Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '11, (pp. 325-334).ACM Press. doi: 10.1145/2039370.2039420.

Che, Y., Li, H., & Wang, X. (2010). Spintronic devices: From memory to memristor. In 2010 International Conference on Communications, Circuits and Systems (ICCCAS), (pp. 811-816).IEEE. doi: 10.1109/icccas.2010.5581868.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., & Zhang, T. (2010). Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. In Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design - ISLPED '10, (pp. 1-6).ACM Press. doi: 10.1145/1840845.1840847.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., & Zhang, T. (2010). A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM). In Proceedings -Design, Automation and Test in Europe, DATE, (pp. 148-153).

Chen, Y., Wang, X., Sun, Z., & Li, H. (2010). The application of spintronic devices in magnetic bio-sensing. In 2nd Asia Symposium on Quality Electronic Design (ASQED), (pp. 230-234).IEEE. doi: 10.1109/asqed.2010.5548244.

Chen, Y., Wang, X., Zhu, W., Li, H., Sun, Z., Sun, G., & Xie, Y. (2010). Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization. In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, (pp. 1109-1112).IEEE. doi: 10.1109/mwscas.2010.5548848.

Chen, Y., Wei Tian, Li, H., Xiaobin Wang, & Wenzhong Zhu. (2010). Scalability of PCMO-based resistive switch device in DSM technologies. In 2010 11th International Symposium on Quality Electronic Design (ISQED), (pp. 327-332).IEEE. doi: 10.1109/isqed.2010.5450447.

Hai Li, & Yiran Chen. (2010). Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture. In 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, (pp. 1-4).IEEE. doi: 10.1109/mwscas.2010.5548590.

Sun, G., Joo, Y., Chen, Y., Niu, D., Xie, Y., Chen, Y., & Li, H. (2010). A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture, (pp. 141-152).IEEE. doi: 10.1109/hpca.2010.5416650.

Sun, Z., Li, H., Chen, Y., & Wang, X. (2010). Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement. In 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (pp. 432-437).IEEE. doi: 10.1109/iccad.2010.5653720.

Li, H., Xi, H., Chen, Y., Stricklin, J., Wang, X., & Zhang, T. (2009). Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration. In 2009 IEEE Computer Society Annual Symposium on VLSI, (pp. 217-222).IEEE. doi: 10.1109/isvlsi.2009.17.

Chen, Y., Wang, X., Li, H., Liu, H., & Dimitrov, D.V. (2008). Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). In 9th International Symposium on Quality Electronic Design (isqed 2008), (pp. 684-690).IEEE. doi: 10.1109/isqed.2008.4479820.

Dong, X., Wu, X., Sun, G., Xie, Y., Li, H., & Chen, Y. (2008). Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In Proceedings - Design Automation Conference, (pp. 554-559). doi: 10.1109/DAC.2008.4555878.

Chen, Y., Li, H., Li, J., & Koh, C.K. (2007). Variable-latency adder (VL-adder). In Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07, (pp. 195-200).ACM Press. doi: 10.1145/1283780.1283822.

Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, & Hai Li. (2007). VOSCH: Voltage scaled cache hierarchies. In 2007 25th International Conference on Computer Design, (pp. 496-503).IEEE. doi: 10.1109/iccd.2007.4601944.

Li, H., Chen, Y., Roy, K., & Koh, C.K. (2006). SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006, (pp. 158-163).

Chen, Y., Li, H., Roy, K., & Koh, C.K. (2005). Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design. In Proceedings of the International Symposium on Low Power Electronics and Design, (pp. 115-118).

Hai Li, Bhunia, S., Chen, Y., Vijaykumar, T.N., & Roy, K. (2003). Deterministic clock gating for microprocessor power reduction. In The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 12, (pp. 113-122).IEEE Comput. Soc. doi: 10.1109/hpca.2003.1183529.

Research interests

Architecture/circuit/device...
Hardware implementation and...
Memory design and architecture
Neuromorphic architecture for...