Pitt | Swanson Engineering
Chen, Yiran
Electrical and Computer Engineering
Chen, Yiran
Faculty
Associate Professor
Office: PSVR 4173
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Ph.D. in Electrical and Computer engineering, Purdue University, 2005

M.S. in Electronic Engineering, Tsinghua University, 2001

B.S. in Electronic Engineering, Tsinghua University, 1998

Embedded systems and mobile applications

Emerging memory and sensing technologies

Mobile technology and human-machine interaction, security

Nano-electronic devices (silicon and non-silicon)

(2013) NSF CAREER Award.

(2013) Best Paper Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper titled "Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache".

(2012) 49th Design Automation Conference A. Richard Newton Scholarship for Ph.D. student Wujie Wen.

(2011) 3. Two Times Air Force Visiting Faculty Research Program (VFRP) Fellowship, AFRL/RIB, Rome, NY, 2011, 2012. (Selected extensions of $10,000 and $8000 grants are also approved for Sep.┬┐Dec. 2011, and 2012, respectively).

(2011) Best Paper Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper titled "Geometry Variations Analysis of TiO2 Thin Film and Spintronic Memristors".

(2010) 7. Best Paper Nomination, Design, Automation & Test in Europe Conference and Exhibition (DATE) for the paper titled "A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)".

(2010) 6. Best Paper Award, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) for the paper titled "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM".

(2010) Best Paper Nomination, the 11th International Symposium on Quality Electronic Design (ISQED) for the paper titled "Scalability of PCMO-based Resistive Switch Device in DSM Technologies".

(2008) Best Paper Award, the 9th International Symposium on Quality Electronic Design (ISQED) for paper titled "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)".

(2007) Finalists of Prestigious 2007 DesignVision Awards for PrimeTimeVX, International Engineering Cons.

(2006) The hot 100 products of 2006 for PrimeTimeVX, EDN (www.edn.com).

(2006) PrimeTimeVX - EDN 100 Hot Products Distinction, Synopsys Inc..

(2005) Best Paper Nomination, the 6th International Symposium on Quality Electronic Design (ISQED) for the paper titled "Power Supply Noise-aware Scheduling and Allocation for DSP Synthesis".

Chen, X., Chen, Y., Ma, Z., Fernandes, F., and Xue, J., 2013, "Dynamic Tone Mapping on OLED Display Based on Video Classification," International Conference on Computer Aided Design (ICCAD), Manuscript submitted for publication.

Chen, X., Ma, Z., Fernandes, F.C., and Chen, Y., In press, "How is Energy Consumed in Smartphone Display Applications," The International Workshop on Mobile Computing Systems and Applications (HotMobile).

Guo, J., Wen, W., and Chen, Y., In press, "DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems," Design, Automation & Test in Europe (DATE).

Guo, J., Yang, J., Zhang, Y., and Chen, Y., In press, "Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer," Design, Automation & Test in Europe (DATE).

Hu, M., Chen, Y., Qiu, Q., Yang, J., Chen, Y., 2013, "General Realization of Neuromorphic Computing Systems Based on Stochastic Characteristics of Memristive Switches," International Conference on Computer Aided Design (ICCAD), Manuscript submitted for publication.

Hu, M., Li, H., Wu, Q., Rose, G.S., and Chen, Y., In press, "Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems," IEEE Symposium Series on Computational Intelligence (SSCI).

Li, Y., Jones, A., Zhang, Y., Sun, Z., Chen, Y., and Li, H., 2013, "Staying on Target with X-mode STT-RAM Caches for Fast, Low Power and Reliable Computing," International Symposium on Computer Architecture (ISCA), Manuscript submitted for publication.

Liu, B., Hu, M., Huang, T., Li, H., Mao, Z.H., Zhang, W., and Chen, Y., In press, "Digital-Assisted Noise Eliminating Training for Memristor Crossbar-based Analog Neuromorphic Computing Engine," Design Automation Conference (DAC).

Mao, M., Jones, A., and Chen, Y., In press, "Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems," Great Lakes Symposium on VLSI (GLVLSI).

Nixon, K., Chen, X., Mao, Z.H., Li, K., and Chen, Y., 2013, "The Invisible Shield: User Classification and Authentication for Mobile Device Based on Gesture Recognition," Design Automation Conference (DAC), Manuscript submitted for publication.

Wen, W., Mao, M., Kang, S., Mao, M., and Zhu, X., 2013, "CD-ECC: Content-Dependent Error Correction Codes for Combating Asymmetric Nonvolatile Memory Operation Errors," International Conference on Computer Aided Design (ICCAD), Manuscript submitted for publication.

Chen, Y., Guo, J., and Sun, Z., "CPU-GPU System Designs for High Performance Computing," To appear in in High Performance Semantic Cloud Auditing; (to appear), B. Choi, and K. Han, eds., Springer.

Chen, Y., Wong, W., Li, H., Koh, C.K., Zhang, Y., and Wen, W., "On-chip Caches built on Multi-Level Spin-Transfer Torque RAM Cells and Its Optimizations," To appear in ACM Journal on Emerging Technologies in Computing Systems (JETC).

Hu, M., Li, H., Chen, Y., Wu, Q., Rose, G., and Linderman, R., "Hardware Realization of Neural Network Using Memristor Crossbar Arrays," Manuscript submitted for publication.

Li, J., Shi, L., Li, Q., Xue, C., Chen, Y., and Xu, Y., "Low-Energy Volatile STT-RAM Cache Design Using Cache Coherence Enabled Adaptive Refresh," ACM Transactions on Design Automation of Electronic Systems (TODAES), Manuscript submitted for publication.

Li, Q., Li, J., Shi, L., Xue, C.J., Chen, Y., and He, Y., "Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache," IEEE Transactions on Computers (TC), Manuscript submitted for publication.

Liu, B., Chen, Y., Wysocki, B., and Huang, T., "The Circuit Realization of a Neuromorphic Computing System with Memristor-based Synapse Design," Neural Processing Letters (NPL), Manuscript submitted for publication.

Niu, L., MEdina, L., and Chen, Y., "Reliability-Aware Energy Minimization for Real-Time Embedded Systems with Window-Constraints," To appear in ACM SIG on Embedded Systems Review (SIGBED).

Nixon, K., Chen, Y., Mao, Z.H., and Li, K., "User Classification and Authentication for MOBILE Device Based on Gesture Recognition," To appear in in Network Science and Cybersecurity (to appear), R. Pino, ed., Springer.

Zhang, L., Chen, Z., Yang, J.J., Wysocki, B., and McDonald, N., "A Compact Modeling of TiO2-TiO2-x Memristor," Applied Physics Letters (APL), Manuscript submitted for publication.

Zhang, Y., Wen, W., and Chen, Y., "Asymmetry in STT-RAM Cell Operations," To appear in in Emerging Memory Technologies: Design, Architecture, and Applications; (to appear), Y. Xie, ed., Springer.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., and Li, H., "Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices," ACM Transactions on Design Automation of Electronic Systems (TODAES), major revision, Manuscript submitted for publication.

Chen, Y., 2013, "What is Nueromorphic Computing."

Li, Q., Li, J., Shi, L., Xue, C.J., Chen, Y., and He, Y., 2013, "ompiler-Assisted Refresh Minimization for Volatile STT-RAM Cache," 17th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 273-278.

Nixon, K., Mao, Z.H., Li, K., and Chen, Y., 2013, "Mobile User Classification and Authorization Based on Gesture Usage Recognition," 18th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 384-389.

Wen, W., and Chen, Y., 2013, "Loadsa: A Yield-Driven Top-Down Design Method for STT-RAM Array," 17th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 291-296.

Zhang, Y., Bi, X., Wen, W., and Chen, Y., 2013, "STT-RAM Design Considering Probabilistic and Asymmetric MTJ Switching," IEEE International Symposium on Circuits and Systems (ISCAS).

Zhang, Y., Wen, W., and Chen, Y., 2013, "STT-RAM Cell Design Considering MTJ Asymmetric Switching," SPIN, no.3, 1240007 (9 pages).

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., and Zhang, T., 2012, "A 130nm 1.2V/3.3V 16Kb Spin-Transfer Torque Random Access Memory with Nondestructive Self-Reference Sensing Scheme," IEEE Journal of Solid State Circuits (JSSC), no.2, pp. 560-573.

Chen, Y., Li, H., Xie, Y., and Niu, D., 2012, "Low Power Design of Emerging Memory Technologies," in Handbook of Energy-Aware and Green Computing; ISBN: 978-14-398-5040-4, I. Ahmad, and S. Ranka, eds., CRC Press.

Chen, Y., Xue, J., Chen, X., and Zhao, M., 2012, "Mobile Devices User - The Subscriber and also the Publisher of Real-Time OLED Display Power Management Plan," International Conference on Computer Aided Design (ICCAD), pp. 687-690.

Chen, Y., Zhang, Y., and Wang, P., 2012, "Probabilistic Design in Spintronic Memory and Logic Circuit," 17th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 323-328.

Bi, X., Li, H., Chen, Y., and Pino, R., 2012, "Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference," Design, Automation & Test in Europe (DATE), pp. 1301-1306.

Chen, X., Liu, B., Xue, J., Guo, X., and Chen, Y., 2012, "Multi-level Cell STT-RAM: Is It Realistic or Just a Dream?," International Conference on Computer Aided Design (ICCAD), pp. 516-522.

Chen, X., Zeng, J., Li, H., Zhang, W., and Chen, Y., 2012, "Fine-grained Dynamic Voltage Scaling on OLED Display," 17th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 807-812.

Chen, X., Zhao, J., Chen, Y., and Xue, C.J., 2012, "Quality-retaining OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices," Design Automation Conference (DAC), pp. 1000-1005.

Hu, M., Li, H., Wu, Q., Rose, G.S., and Chen, Y., 2012, "Memristor Crossbar Based Hardware Realization of BSB Recall Function," 2012 International Joint Conference on Neural Networks (IJCNN), pp. 1-7.

Li, Y., Chen, Y., and Jones, A.K., 2012, "A Software Approach for Combating Asymmetries of Non-Volatile Memories," International Symposium on Low Power Electronics and Design (ISLPED), pp. 191-196.

Li, Y., Chen, Y., and Jones, A.K., 2012, "Combating Write Penalties Using Software Dispatch for On-chip MRAM Integration," IEEE Embedded System Letters (ESL), no.4, pp. 82-85.

Liu, B., Chen, Y., Wysocki, B., and Huang, T., 2012, "The Circuit Realization of a Neuromorphic Computing System with Memristor-based Synapse Design," International Conference on Neural Information Processing (ICONIP), pp. 357-365.

Pino, R., Li, H., Chen, Y., Hu, M., and Liu, B., 2012, "Statistical Memristor Modeling and Case Study in Neuromorphic Computing," Design Automation Conference (DAC), pp. 585-590.

Shao, Z., Liu, Y., Chen, Y., and Li, T., 2012, "Utilizing PCM for Energy and Power Optimization in Embedded Systems," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 398-403.

Sun, G., Zhang, Y., Wang, Y., and Chen, Y., 2012, "Improving Energy Efficiency of Write-Asymmetric Memories by Log Style Write," International Symposium on Low Power Electronics and Design (ISLPED), pp. 173-178.

Sun, Z., Chen, X., Zhang, Y., Li, H., and Chen, Y., 2012, "Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder," ACM Journal on Emerging Technologies in Computing Systems (JETC), no.2, article 13.

Sun, Z., Li, H., Chen, Y., and Wang, X., 2012, "Voltage Driven Non-Destructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.11, pp. 2020-2030.

Wang, P., Zhang, W., Joshi, R., Kanj, R., and Chen, Y., 2012, "A Thermal and Process Variation Aware MTJ Switching Model and Its Applications in Soft Error Analysis," International Conference on Computer Aided Design (ICCAD), pp. 720-727.

Wen, W., Zhang, Y., Chen, Y., Wang, Y., and Xie, Y., 2012, "Memristor Crossbar Based Hardware Realization of BSB Recall Function," Design Automation Conference (DAC), pp. 1191-1196.

Zhang, Y., Chen, Y., Li, Y., and Jones, A., 2012, "Asymmetry of MTJ Switching and Its Implication to the STT-RAM Designs," Deisign, Automation & Test in Europe (DATE), pp. 1313-1318.

Zhang, Y., Wen, W., and Chen, Y., 2012, "The Prospect of STT-RAM Scaling from Readability Perspective," IEEE Transaction on Magnetics (TMAG), no.11, pp. 3035-3038.

Zhang, Y., Zhang, L., Wen, W., Sun, G., and Chen, Y., 2012, "Multi-level Cell STT-RAM: Is It Realistic or Just a Dream?," International Conference on Computer Aided Design (ICCAD), pp. 526-532.

Chen, Y., and Li, H., 2011, "Emerging Sensing Techniques for Emerging Memories," 16th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 204-210.

Chen, Y., Wong, W.F., Li, H., and Koh, C.K., 2011, "Processor Caches built using Multi-Level Spin-Transfer Torque RAM Cells," International Symposium on Low Power Electronics and Design (ISLPED), pp. 73-78.

Dong, X., Wu, X., Xie, Y., Chen, Y., and Li, H., 2011, "Stacking Magnetic Random Access Memory atop Microprocessors: An Architecture-Level Evaluation," IET Computers & Digital Techniques (IET-CDT), no.3, pp. 213-220.

Hu, M., Li, H., Chen, Y., and Wang, X., 2011, "Spintronic Memristor: Compact Model and Statistical Analysis," Journal of Low Power electronics (JOLPE), no.2, pp. 234-244.

Hu, M., Li, H., Chen, Y., Wang, X., and Pino, R.E., 2011, "Geometry Variations Analysis of TiO2-based and Spintronic Memristors," 16th Asia and South Pacific Design Automation Conference (ASPDAC), pp. 25-30.

Li, H., and Chen, Y., 2011, "Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing; ISBN: 978-14-398-0745-3," CRC Press.

Li, H., Wang, X., Ong, Z.L., Wong, W.F., Zhang, Y., Wang, P., and Chen, Y., 2011, "Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement," IEEE Transaction on Magnetics (TMAG), no.10, pp. 2356-2359.

Wang, P., Wang, X., Zhang, Y., Li, H., Levitan, S., and Chen, Y., 2011, "Non-persistent Error Optimization in Spin-MOS Logic and Storage Circuitry," IEEE Transaction on Magnetics (TMAG), no.10, pp. 3860-3863.

Xu, W., Sun, H., Wang, X., Chen, Y., and Zhang, T., 2011, "Design of Last-Level On-Chip Cache using Spin-Torque Transfer RAM (STT-RAM)," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no.3, pp. 483-493.

Xue, J., Zhang, Y., Chen, Y., Sun, G., Yang, J.J., and Li, H., 2011, "Emerging Non-Volatile Memories: Opportunities and Challenges," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 325-334.

Zhang, Y., Wang, X., and Chen, Y., 2011, "STT-RAM Cell Design Optimization for Persistent and Non-Persistent Error Rate Reduction: A Statistical Design View," International Conference on Computer Aided Design (ICCAD), pp. 471-477.

Zhang, Y., Wang, X., Li, H., and Chen, Y., 2011, "STT-RAM Cell Optimization Considering Process Variations," IEEE Transaction on Magnetics (TMAG), no.10, pp. 2962-2965.

Zhu, W., Li, H., Chen, Y., and Wang, X., 2011, "Current Switching in MgO-based Magnetic Tunneling Junctions," IEEE Transactions on Magnetics (TMAG), no.1 part 2, pp. 156-160.

Chen, Y., and Li, H., 2010, "Patents Relevant to Cross-point Memory Array."

Chen, Y., Li, H., and Wang, X., 2010, "Spintronic Devices: from Memory to Memristor," International Conference on Communications, Circuits and Systems (ICCCAS), pp. 961-963.

Chen, Y., Li, H., Chen, C.K., Roy, K., Li, J., and Sun, G., 2010, "Variable-Latency Adder (VL-Adder): New Arithmetic Circuit Design Practice for Low Power and NBTI Tolerance," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.11, pp. 1621-1624.

Chen, Y., Li, H., Sun, Z., Wang, X., Zhu, W., Sun, G., and Xie, Y., 2010, "Access Scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and Its Optimization," 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1109-1112.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., and Zhang, T., 2010, "A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)," Design, Automation & Test in Europe (DATE), pp. 148-153.

Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., and Zhang, T., 2010, "Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM," International Symposium on Low Power Electronics and Design (ISLPED), pp. 1-6.

Chen, Y., Tian, W., Li, H., Wang, X., and Zhu, W., 2010, "PCMO Device with High Switching Stability," IEEE Electron Device Letters (EDL), no.8, pp. 866-868.

Chen, Y., Tian, W., Li, H., Wang, X., and Zhu, W., 2010, "Scalability of PCMO-based Resistive Switch Device in DSM Technologies," International Symposium on Quality Electronic Design (ISQED), pp. 327-332.

Chen, Y., Wang, X., Li, H., and PArk, J., 2010, "Applications of TMR Devices in Solid State Circuits and Systems," International SoC Design Conference (ISOCC), S14-2.

Chen, Y., Wang, X., Li, H., Xi, H., Zhu, W., and Yan, Y., 2010, "Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.12, pp. 1724-1734.

Chen, Y., Wang, X., Sun, Z., and Li, H., 2010, "The Application of Spintronic Devices in Magnetic Bio-sensing," Asia Symposium on Quality Electronic Design (ASQED), pp. 230-234.

2010.

Li, H., and Chen, Y., 2010, "Emerging Non-Volatile Memory Technologies - From Materials, to Device, Circuit, and Architecture," 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4.

Niu, D., Chen, Y., and Xie, Y., 2010, "Low-power Dual-element Memristor-Based Memory Design," International Symposium on Low Power Electronics and Design (ISLPED), pp. 25-30.

Niu, D., Chen, Y., Xu, C., and Xie, Y., 2010, "Impact of Process Variations on Emerging Memristor," Design Automation Conference (DAC), pp. 877-882.

Sun, G., Joo, Y., Chen, Y., Xie, Y., Chen, Y., and Li, H., 2010, "A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement," International Symposium on High-Performance Computer Architecture (HPCA), pp. 141-152.

Sun, Z., Li, H., Chen, Y., and Wang, X., 2010, "Variation Tolerant Sensing Scheme of Spin-Transfer Torque Memory for Yield Improvement," International Conference on Computer Aided Design (ICCAD), pp. 432-437.

Wang, X., Chen, Y., and Zhang, T., 2010, "Magnetization Switching in Spin Torque Random Access Memory: Challenges and Opportunities; Chapter 9," in CMOS Processors and Memories; ISBN: 978-90-481-9215-1, K. Iniewski, ed., Springer.

Wang, X., Chen, Y., Gu, Y., and Li, H., 2010, "Spintronic Memristor Temperature Sensor," IEEE Electron Device Letters (EDL), no.1, pp. 20-22.

Wang, X., and Chen, Y., 2010, "Patents Relevant to Spintronic Memristor."

Wang, X., and Chen, Y., 2010, "Spintronic Memristor Devices and Application," Design, Automation & Test in Europe (DATE), pp. 667-672.

Xi, H., Stricklin, J., Li, H., Chen, Y., Wang, X., Zheng, Y., Gao, Z., and Tang, M.X., 2010, "Spin Transfer Torque Memory with Thermal Assist Mechanism: A Case Study," IEEE Transaction on Magnetics (TMAG), no.3, pp. 860-865.

Xu, W., Zhang, T., and Chen, Y., 2010, "Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no.1, pp. 66-74.

Chen, Y., 2009, "What is Memristor."

Chen, Y., and Wang, X., 2009, "Compact Modeling and Corner Analysis of Spintronic Memristor," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 7-12.

Chen, Y., Li, H., Chen, C.K., and Roy, K., 2009, "Gated Decap: Gate Leakage Control of On-chip Decoupling Capacitors in Scaled Technologies," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.12, pp. 1749-1752.

Koh, C.K., Wong, W.F., Chen, Y., and Li, H., 2009, "The Salvage Cache: A Fault-tolerant Cache Architecture for Next-generation Memory Technologies," International Conference on Computer Design (ICCD), pp. 268-274.

Koh, C.K., Wong, W.F., Chen, Y., and Li, H., 2009, "Tolerating Process Variations in Large, Set Associative Caches: The Buddy Cache," ACM Transactions on Architecture and Code Optimization (TACO), no.8, 34 pages.

Li, H., and Chen, Y., 2009, "An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures," Design, Automation & Test in Europe (DATE), pp. 731-736.

Li, H., Xi, H., Chen, Y., Wang, X., and Zhang, T., 2009, "Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 217-222.

Sun, G., Dong, X., Xie, Y., Li, J., and Chen, Y., 2009, "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs," 14th International Sympsosium on High-Performance Computer Architecture (HPCA), pp. 239-249.

Wang, X., Chen, Y., Xi, H., Li, H., and Dimitrov, D.V., 2009, "Spintronic Memristor through Spin Torque Induced Magnetization Motion," IEEE Electron Device Letters (EDL), no.3, pp. 294-297.

Xi, H., Wang, X., Chen, Y., and Ryan, P., 2009, "Ordering of Magnetic Nanoparticles in Bilayer Structures," Journal of Physics D: Applied Physics, no.015006.

Xu, W., Chen, Y., Wang, X., and Zhang, T., 2009, "Improving STT MRAM Storage Density through Smaller-Than-Worst-Case Transistor Sizing," Design Automation Conference (DAC), pp. 87-90.

Chen, Y., Wang, X., Li, H., Liu, H., and Dimitrov, D., 2008, "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)," International Symposium on Quality Electronic Design (ISQED), pp. 684-690.

Dong, X., Wu, X., Sun, G., Chen, Y., Li, H., and Xie, Y., 2008, "Circuit and Microarchitecture Evaluation of Magnetic RAM (MRAM) as a Universal Memory Replacement," Design Automation Conference (DAC), pp. 554-559.

Wang, X., Chen, Y., Li, H., Liu, H., and Dimitrov, D., 2008, "Spin Torque Random Access Memory down to 22nm Technology," IEEE Transaction on Magnetics (TMAG), no.11, pp. 2479-2482.

Xu, W., Zhang, T., and Chen, Y., 2008, "Spin-Transfer Torque Magnetoresistive Content Addressable Memory (CAM) Cell Structure Design with Enhanced Search Noise Margin," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1898-1901.

Chen, Y., Li, H., Li, J., and Koh, C.K., 2007, "Variable-latency Adder (VL-Adder): New Arithmetic Circuit Design Practice to Overcome NBTI," International Symposium on Low Power Electronics and Design (ISLPED), pp. 195-200.

Koh, C.K., Wong, W.F., Chen, Y., and Li, H., 2007, "VOSCH: Voltage Scaled Cache Hierarchies," International Conference on Computer Design (ICCD), pp. 496-503.

Li, H., Koh, C.K., Balakrishnan, V., and Chen, Y., 2007, "Statistical Timing Analysis Considering Spatial Correlations," International Symposium on Quality Electronic Design (ISQED), pp. 102-107.

Li, H., Chen, Y., Roy, K., and Koh, C.K., 2006, "SAVS: A Self-adaptive Variable Supply-voltage Technique for Process-tolerant and Power-efficient Multi-issue Superscalar Processor Design," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 158-163.

Chen, Y., Li, H., Roy, K., and Koh, C.K., 2005, "Gated Decap: A Technique to Reduce Gate Leakage in Decoupling Capacitors in Scaled Technologies," IEEE Custon Integrated Circuits Conference (CICC), pp. 775-778.

Chen, Y., Roy, K., and Koh, C.K., 2005, "Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no.1, pp. 75-85.

Kung, D., Chen, Y., and Roy, K., 2005, "Power Supply Noise-aware Scheduling and Allocation for DSP Synthesis," International Symposium on Quality Electronic Design (ISQED), pp. 48-53.

Lam, W.C., Jain, J., Koh, C.K., Balakrishnan, V., and Chen, Y., 2005, "Statistical based link insertion for robust clock network design," International Conference on Computer-Aided Design (ICCAD), pp. 588-591.

Chen, Y., Roy, K., and Koh, C.K., 2004, "Architectural and Physical Level Techniques for Power Supply Noise Suppression."

Chen, Y., Roy, K., and Koh, C.K., 2004, "Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 893-898.

Li, H., Bhunia, S., Chen, Y., Vijaykumar, T.N., and Roy, K., 2004, "DCG: Deterministic Clock Gating For Low-Power Microprocessor Design," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, no.3, pp. 245-254.

Chen, Y., Roy, K., and Koh, C.K., 2003, "Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors," International Symposium on Low Power Electronics and Design (ISLPED), pp. 229-234.

Koh, C.K., Balakrishnan, V., Roy, K., Zhong, G., Chen, Y., Li, H., and Yang, Y.C., 2003, "Model Analysis of Large-Scale VLSI Systems."

Koh, C.K., Roy, K., Zhao, S., Zhong, G., and Chen, Y., 2003, "Power Supply Noise Modeling and Synthesis."

Li, H., Bhunia, S., Chen, Y., Vijaykumar, T.N., and Roy, K., 2003, "Deterministic Clock Gating for Microprocessor Power Reduction," 9th International Symposium on High-Performance Computer Architecture (HPCA), pp. 113-122.

Chen, Y., Balakrishnan, V., Koh, C.K., and Roy, K., 2002, "Model Reduction in the Time-domain using Laguerre Polynomials and Krylov Methods," Design, Automation & Test in Europe (DATE), pp. 931-937.

Chen, Y., Zhang, L., and Fan, C., 2002, "Beat Phenomena and Its Suppression in Cascaded Gain-clamped EDFA," Chinese Journal of Laser, no.3, pp. 243-249.

Koh, C.K., Balakrishnan, V., Roy, K., Su, Q., and Chen, Y., 2002, "Efficient Analysis of Large-Scale VLSI Systems."

Chen, Y., 2001, "Easy to learn PowerPoint 2000 (Chinese Version) ISBN: 7-80134-578-9," Aviation Industry Press (AIP), Beijing.

Chen, Y., Zhang, L., and Fan, C., 2001, "Beat Phenomena and Its Suppression in Cascaded Gain-clamped EDFA," IEEE Proceeding of Optoelectronics, no.3, 6/2001, 161-164.

Li, H., Agrawal, A., Chen, Y., and Roy, K., 2001, "DRG-Cache: A Single Vt Low Leakage Cache for Deep Submicron."

Chen, Y., Zhang, L., Jiang, Z., Yu, Q., and Fan, C., 2000, "Suppression of Stimulated Brillouin Scattering induced by the Compensating Signal in All-Optical Gain-Clamped EDFA," International Conference on Communication Technology (ICCT), pp. 203-205.

Zhou, P., Zhao, B., Zhang, Y., Yang, J., and Chen, Y., "A Memristor-based Policy Selection Framework for Cache Replacement," ACM Journal on Emerging Technologies in Computing Systems (JETC), major revision.

Chen, X., Chen, Y., Ma, Z., Fernandes, F., and Xue, J., 2013, "Dynamic Tone Mapping on OLED Display Based on Video Classification," 50th Design Automation Conference (DAC).

Hu, M., Li, H., Rose, G., Wu, Q., and Chen, Y., 2013, "Training Scheme Analysis for Memristor-Based Neuromorphic Design," International Workshop on Neuromorphic and Brain-Based Computing Systems (NeuComp).

Li, J., Shi, L., Li, Q., Xue, C.J., Chen, Y., and Xu, Y., 2013, "Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM," Design, Automation & Test in Europe (DATE).

Mao, M., Li, H., Jones, A., Xue, J., and Chen, Y., 2013, "Dynamic Prefetch Aggressiveness Tuning for STT-RAM-based Last-level Cache," 4th Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW4).

Chen, Y., 2012, "Emerging Applications of Next-generation Nonvolatile Memory Technologies," University Relationship Colloquium, Qualcomm Inc., San Diego.

Chen, Y., 2012, "Emerging NVM Enabled Computing Architecture - From Evolution to Revolution," 8th Annual Full Day Symposium Emerging Non-Volatile Memory Technologies, hosted by IEEE San Francisco Bay Area Nanotechnolgoy Coucil Chapter, Santa Clara, CA.

Chen, Y., 2012, "Introduction to Development of Android Smartphone Applications (Apps)," U.S. Air Force Research Lab, Rome, NY.

Chen, Y., 2012, "Stay Spinning, Stay Cool!," Departmental colloquium, Department of Electrical & Computer Engineering, University of Pittsburgh, Pittsburgh.

Chen, Y., 2012, "Stay Spinning, Stay Cool!," Electronic Engineering Department, Tsinghua University, Beijing, China.

Chen, Y., 2012, "Stay Spinning, Stay Cool!," Information Engineering School, Zhengzhou University, Henan, China.

Chen, Y., and Li, H., 2012, "Perspective of Nonvolatile Memories in SoC and Computing Systems," Lenovo Corporate Research and Development, Beijing, China.

Chen, Y., and Li, H., 2012, "STT-RAM Research of Pitts and NYU-Poly Team," Samsung, Dongtan, Korea.

2012, "Centaur: Bio-inspired Ultra Low-Power Hybrid Embedded Computing Engine Beyond One TeraFlops/Watt," International Conference on Neural Information Processing (ICONIP), Doha, Qatar.

2012, "Prediction of STT-RAM Parameters for 2012-2025," ERD Workshop on Emerging Architectures for Storage Class Memory, Monterey, CA.

2012, "Research on NAND Flash Based Storage System Reliability Enhancement," Fusion-io Inc., San Jose, CA.

2012, "The Applications of Spintronic Memory in Microprocessors," Flash Memory Summit, Santa Clara, CA.

2012, "User Classification and Authorization Based on Gesture Usage Recognition," Network Science and Reconfigurable Systems for Cybersecurity (NSRSC) Conference, Washington D.C..

Niu, L., MEdina, L., and Chen, Y., 2012, "Reliability-Aware Energy Minimization for Real-Time Embedded Systems with Window-Constraints," IEEE Real-Time Systems Symposium (RTSS).

Wang, P., and Chen, Y., 2012, "Robustness of MTJ Switching in STT-RAM under Radiation Attack," IEEE International Magnetics Conference (InterMag), HB-07.

Wang, P., Wu, J., and Chen, Y., 2012, "MTJ-based Nonvolatile Latch Design for Standby System," The Non-Volatile Memories Workship 2012.

Zhang, Y., Wen, J., and Chen, Y., 2012, "The Prospect of STT-RAM Scaling from Read ability Perspective," IEEE International Magnetics Conference (InterMag), BB-03.

Zhao, B., Yang, J., Zhang, Y., Chen, Y., and Li, H., 2012, "Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices," Design, Automation & Test in Europe (DATE), pp. 1451-1454.

Zhao, M., Chen, X., Chen, Y., and Xue, J., 2012, "Online OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices," IEEE Real-Time Systems Sympsium (RTSS).

Chen, Y., 2011, "Current Research and Its Trend of Emerging Memory Technologies," The CCF Advanced Disciplines Lectures, Hangzhou, China, May 8, 2011 and Hong Kong Polytechnic University, Hong Kong.

Chen, Y., 2011, "Integrating Emerging Memory atop CMP: Opportunities and Challenges from a Designer Perspective," 3D Integration Workshop For High Performance Computing Systems, Abu Dhabi, United Arab Emirates.

Chen, Y., 2011, "Resistive Memory and Systems," Microelectric Institute, Tsinghua University.

Chen, Y., 2011, "Spintronic Memristor: Intelligent Device for Storing, Sensing and Computing," Spintronic Workshop, Qualcomm Inc., San Diego.

Chen, Y., 2011, "The applications of STT-RAM in Microarchitecture," Institute of Computing Technology, Chinese Academy of Sciences.

Chen, Y., and Li, H., 2011, "STT-RAM Research of University of Pittsburgh Poly-New York University Team," Avalanche Technology, Fremont, CA.

Chen, Y., Wang, X., Wong, W.F., and Li, H., 2011, "Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement," The Non-Volatile Memories Workship 2011.

Chen, Y.C., Li, H., Chen, Y., and Pino, R., 2011, "3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory," Design, Automation & Test in Europe (DATE), pp. 1-4.

Hu, M., Li, H., Chen, Y., and Pino, R.E., 2011, "Statistical Model of TiO2 Memristor," 48th Design Automation Conference (DAC).

Li, H., Wang, X., Ong, Z.L., Wong, W.F., Zhang, Y., Wang, P., and Chen, Y., 2011, "Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement," IEEE International Magnetics Conference (InterMag), AD-02.

Li, Y., Chen, Y., and Jones, A., 2011, "Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching," Workshop on Emerging Supercomputing Technologies (WEST, in conjunction with International Conference on Supercomputing).

Wang, P., Chen, X., Chen, Y., Li, H., Kang, S., Zhu, X., and Wu, W., 2011, "A 1.0V 45nm Nonvolatile Magnetic Latch Design and Its Robustness Analysis," IEEE Custon Integrated Circuits Conference (CICC), pp. 1-4.

Wang, P., Wang, X., Zhang, Y., Li, H., and Chen, Y., 2011, "Spin-MOS Logic and Storage Circuitry Optimization for Non-persistent Error Rate Reduction," IEEE International Magnetics Conference (InterMag), FR-01.

Zhang, Y., Chen, Y., Wang, X., and Li, H., 2011, "STT-RAM Cell Optimization Considering Process Variations," The Non-Volatile Memories Workship 2011.

Zhang, Y., Wang, X., Li, H., and Chen, Y., 2011, "STT-RAM Cell Optimization Considering Process Variations," IEEE International Magnetics Conference (InterMag), CC-05.

Zhou, P., Zhao, B., Yang, J., Zhang, Y., and Chen, Y., 2011, "MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement," 20th international conference on Parallel Architectures and Compilation Techniques (PACT).

Chen, Y., 2010, "Applications of Emerging Memory in Modern Computer Architecture," School of Computing, National University of Singapore, and Nanyang Technology University.

Chen, Y., 2010, "Emerging Resistive Device - an Alternative Path to Continue Moore's Law," CSE Seminar Series, Department of Computer Science and Engineering, Notre Dame University, Notre Dame, IN.

Chen, Y., 2010, "Resistive Memory and Systems," Workshop on Technology-Architecture Interaction: Emerging Technologies and their Impact on Computer Architecture (Held in conjunction with 43rd Annual IEEE/ACM International Symposium on Microarchitecture), Atlanta.

Chen, Y., 2010, "Spintronic devices - An Alternative Path to Continue Moore's Law," Dalian Mini-Colloquia of IEEE Electron Device Society, Dalian, China.

Sun, Z., Li, H., Chen, Y., and Wang, X., 2010, "Magnetic Bio-sensing based on Spintronic Memristor," International Workshop on Biomedical System Design.

Chen, Y., 2009, "Emerging Resistive Memory - the Next Breakthrough in Computing System," Department of Computer Science and Engineering's Colloquium, Pennsylvania State University, State College, PA.

Chen, Y., 2008, "Emerging Non-volatile Memory: Spin-Transfer Torque Memory and Resistive Memory," Department of Electrical and Computer Engineering's Colloquium, University of Minnesota, Minneapolis, MN.

Chen, Y., 2008, "Emerging Non-volatile Memory: Spin-Transfer Torque Memory and Resistive Memory," Department of Electronic Engineering, Tsinghua University, Beijing, China.

Wang, X., Chen, Y., Li, H., Liu, H., and Dimitrov, D., 2008, "Spin Torque Random Access Memory down to 22nm Technology," IEEE International Magnetics Conference (Intermag), GD-03.

Chen, Y., Li, H., Roy, K., and Koh, C.K., 2005, "Cascaded Carry-Select Adder (C2SA): A New Structure for Low-Power CSA Design," International Symposium on Low Power Electronics and Design (ISLPED), pp. 115-118.

Chen, Y., 2004, "Resources Balancing: A Technique for Minimization of Current Surge in Microprocessor," 7th SIGDA Ph.D. Forum at Design Automation Conference, San Diego, CA.

Chen, Y., 2003, "Low Power CPU Design," Institute of Computing Technology, Chinese Academy of Sciences.

Chen, Y., 2003, "System Level Low Power CPU Design," Department of Electronic Engineering, Tsinghua University.

Liu, H., Lu, Y., Carter, A., and Chen, Y., "Memory Array with Read Reference Voltage Cells," 7,755,923.

Chen, Y., Li, H., Liu, H., Huang, H., and Lu, Y., "Temperature Dependent Method of Reading ST-RAM," 7,755,965.

Wang, X., Chen, Y., Dimitrov, D., Liu, H.Wang, X., "Diode Assisted Switching Spin-Transfer Torque Memory Unit," 7,804,709.

Zhu, W., Chen, Y., Dimitrov, D., and Wang, X., "Spin-transfer Torque Memory Self-reference Read and Write Assist Methods," 7,813,168.

Zhu, W., Chen, Y., Wang, X., Gao, Z., Xi, H., and Dimitrov, D., "Spin-transfer Torque Memory Self-reference Read and Write Assist Methods," 7,826,260.

Zhu, W., Li, H., Chen, Y., Wang, X., Huang, H., and Xi, H., "Memory Cells with Enhanced Read and Write Sense Margins," 7,852,660.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, R., and Liu, H., "Memory Cell with Proportional Current Self-Reference Sensing," 7,852,665.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., "Write Current Compensation Using Word Line Boosting Circuitry," 7,855,923.

Li, H., Chen, Y., Liu, H., and Wang, X., "Static Source Plane in ST-RAM," 7,859,891.

Zhu, W., Lu, Y., Wang, X., Chen, Y., Wang, A., Lou, X., and Xi, H., "Asymmetric Write Current Compensation," 7,881,096.

Dimitrov, D., Heinonen, O., Chen, Y., Xi, H., and Lou, X., "Electronic Devices Utilizing Spin Torque Transfer To Flip Magnetic Orientation," 7,933,146.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Simultaneously Writing Multiple Addressable Blocks of User Data to A Resistive Sense Memory Cell Array," 7,944,729.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Resistive Sense Memory Array with Partial Block Update Capability," 7,944,731.

Chen, Y., Setiadi, D., Li, H., Xi, H., and Liu, H., "Generic Non-volatile Service Layer," 7,966,581.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., "Write Current Compensation Using Word Line Boosting Circuitry," 8,009,457.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Bit Set Modes for A Resistive Sense Memory Cell Array," 8,040,713.

Wang, X., Chen, Y.Wang, X., Xi, H., Zhong, W., Li, H., and Liu, H., "Magnetic Tunnel Junction and Memristor Apparatus," 8,059,453.

Dimitrov, D., Heinonen, O., Chen, Y., Xi, H., and Lou, X., "Electronic Devices Utilizing Spin Torque Transfer To Flip Magnetic Orientation," 8,077,502.

Li, H., Chen, Y., Liu, H., and Wang, X., "Static Source Plane in ST-RAM," 8,098,516.

Zhu, W., Lu, Y., Wang, X., Chen, Y., Wang, A., Lou, X., and Xi, H., "Asymmetric Write Current Compensation," 8,107,282.

Chen, Y., Li, H., Liu, H., Dimitrov, D., and Wang, X., "Predictive Thermal Pre-Conditioning and Timing Control for Non-volatile Memory Cells," 8,154,914.

Zhu, W., Li, H., Chen, Y., Wang, X., Huang, H., and Xi, H., "Memory Cells with Enhanced Read and Write Sense Margins," 8,199,562.

Chen, Y., Li, H., Liu, H., and Wang, X., "Memory Hierarchy with Non-volatile Filter and Victim Caches.""Memory Hierarchy with Non-volatile Filter and Victim Caches."

Chen, Y., Jin, I., Li, H., Wang, X., Dimitrov, D., and Wang, D., "Programmable Power Source Using Array of Resistive Sense Memory Cells," US Patent Pending, 20100220512.

Li, H., Chen, Y., Wang, X., and Yuan, Y., "Non Volatile Memory Has Increased Sensing Margin," US Patent Pending, 20100128519.

Chen, Y., Setiadi, D., and Ryan, P., "Non-sequential Encoding Scheme for Multi-level Cell (MLC) Memory Cells," US Patent Pending, 13/070,021.

Zhu, W., Chen, Y., Wang, X., Gao, Z., Xi, H., and Dimitrov, D., "Spin-transfer Torque Memory Self-reference Read and Write Assist Methods," 7,961,509.

Chen, Y., Li, H., Liu, H., Lu, Y., and Li, Y., "Transmission Gate-based Spin-transfer Torque memory Unit," 7,974,119.

Chen, Y., Li, H., Liu, H., Wang, R., and Dimitrov, D., "Spin-transfer torque Memory Non-destructive Self-reference Read Scheme," 8,116,123.

Chen, Y., Li, H., Zhu, W., Wang, X., Huang, H., and Liu, H., "Spatial Correlation of Reference Cells in Resistive Memory Array," 8,139,397.

Zheng, Y., Chen, Y., Wang, X., Gao, Z., Dimitrov, D., Zhu, W., and Lu, Y., "Spin-transfer Torque Memory Self-reference Read Method," 8,194,444.

Chen, Y., Li, H., Liu, H., Lu, Y., and Li, Y., "Transmission Gate-based Spin-transfer Torque memory Unit," 8,199,563.

Wang, X., Chen, Y., Dimitrov, D., Liu, H.Wang, X., "Diode Assisted Switching Spin-Transfer Torque Memory Unit," 8,199,569.

Chen, Y., Li, H., Zhu, W., Wang, X., Yan, Y., and Liu, H., "Voltage Reference Generation with Selectable Dummy Regions," 8,203,862.

Chen, Y., Li, H., Zhu, W., Wang, X., Huang, H., and Liu, H., "Resistive Sense Memory Calibration for Self-Reference Read Method," 8,213,215.

Chen, Y., Li, H., Zhu, W., Wang, X., Yan, Y., and Liu, H., "Data Updating in Non-volatile Memory," US Patent Pending, 20100095052.

Zheng, Y., Chen, Y., Wang, X., Gao, Z., and Dimitrov, D., "STRAM with Self-Reference Read Scheme," 7,876,604.

Chen, Y., Li, H., Liu, H., Kim, K., and Huang, H., "Voltage Reference Generation for Resistive Sense Memory Cells," 7,881,094.

Wang, X., Chen, Y.Wang, X., Xi, H., Zhong, W., Li, H., and Liu, H., "Magnetic Tunnel Junction and Memristor Apparatus," 7,898,844.

Dimitrov, D., Heinonen, O., Chen, Y., Xi, H., and Lou, X., "Magnetic Random Access Memory (MRAM) Devices Utilizing Magnetic Flip-flop Structures," 7,933,137.

Chen, Y., Li, H., Liu, H., Lu, Y., and Xue, S., "MRAM Diode Array and Access Method," 7,936,580.

Liu, H., Lu, Y., Carter, A., Chen, Y., Li, H., and Xi, H., "Memory Array with Read Reference Voltage Cells," 7,936,588.

Li, H., Chen, Y., Setiadi, D., Liu, H., and Lee, B., "Defective Bit Scheme for Multi-layer Integrated Memory Device," 7,936,622.

Xi, H., Liu, H., Wang, X., Lu, Y., Chen, Y., Zheng, Y., Dimitrov, D.V., Wang, D., and Li, H., "Variable Write and Read Methods for Resistive Random Access Memory," 7,952,917.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., "Write Current Compensation Using Word Line Boosting Circuitry," 7,974,121.

Zhu, W., Chen, Y., Dimitrov, D., and Wang, X., "Memory Self-reference Read and Write Assist Methods," 8,045,370.

Li, H., Chen, Y., yan, Y., Lee, B., and Wang, R., "Dual Stage Sensing for Non-volatile Memory," 8,050,072.

Li, H., Chen, Y., Liu, H., and Wang, X., "Static Source Plane in ST-RAM," 8,068,359.

Liu, H., Lu, Y., Carter, A., Chen, Y., Li, H., and Xi, H., "Memory Array with Read Reference Voltage Cells," 8,098,513.

Li, H., Chen, Y., Liu, H., Kim, K., and Huang, H., "Spin-Transfer torque Memory Self-reference Read Scheme," 8,116,122.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, R., and Liu, H., "Memory Cell with Proportional Current Self-Reference Sensing," 8,203,899.

Wang, X., Xi, H., Chen, Y., Yan, Y., and Zheng, J., "Domain Wall Movement on Magnetic Strip Tracks," 8,270,204.

Chen, Y., Li, H., Liu, H., Lu, Y., and Xue, S., "MRAM Diode Array and Access Method," 8,289,746.

Wang, X., Lu, Y., Xi, H., Zheng, Y., Chen, Y., Liu, H., Dimitrov, D., Tian, W., and Lee, B., "Non-volatile Memory Cell with Precessional Switching," 8,289,759.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Resistive Sense Memory Array with Partial Block Update Capability," 7,830,700.

Chen, Y., Li, H., Zhu, W., Wang, X., Huang, H., and Liu, H., "Spatial Correlation of Reference Cells in Resistive Memory Array," 7,876,599.

Li, H., Chen, Y., Liu, H., and Wang, X., "Non-volatile Memory Read/Write Verify," 7,916,515.

Wang, X., Lu, Y., Xi, H., Zheng, Y., Chen, Y., Liu, H., Dimitrov, D., Tian, W., and Lee, B., "Non-volatile Memory Cell with Precessional Switching," 7,936,592.

Wang, X., Chen, Y., Dimitrov, D., Liu, H.Wang, X., "Diode Assisted Switching Spin-Transfer Torque Memory Unit," 7,944,742.

Zhu, W., Lu, Y., Wang, X., Chen, Y., Wang, A., Lou, X., and Xi, H., "Asymmetric Write Current Compensation," 8,320,169.

Rivkin, K., Chen, Y., Wang, X., and Xi, H., "Oscillating Current Assisted Spin Torque Magnetic Memory," 7,800,938.

Xi, H., Liu, H., Wang, X., Lu, Y., Chen, Y., Zheng, Y., Dimitrov, D.V., Wang, D., and Li, H., "Variable Write and Read Methods for Resistive Random Access Memory," 7,826,255.

Chen, Y., Li, H., Liu, H., and Wang, X., "Fault-Tolerant Non-volatile Buddy Memory Structure," US Provisional Patent, 20100037102.

Chen, Y., Setiadi, D., and Ryan, P., "Non-sequential Encoding Scheme for Multi-level Cell (MLC) Memory Cells," US Patent Pending.

Carter, A., Chen, Y., Liu, H., and Lu, Y., "Double Source Line-based Memory Array and Memory Cells Thereof," US Patent Pending, 20100118602.

Wang, X., Chen, Y., Dimitrov, D., and Liu, H., "Vertical integrated Memory Structure," US Patent Pending, 20100096611.

Jiao, D., Li, H., Wang, R., Huang, H., and Chen, Y., "Integrated Circuit Active Power Supply Regulation," US Patent Pending, 20100085110.

Chen, Y., Li, H., Zhu, W., Wang, X., huang, H., and Liu, H., "Resistive Sense Memory Calibration for Self-Reference Read Method," 7,898,838.

Chen, Y., Li, H., Liu, H., Dimitrov, D., and Wang, X., "Predictive Thermal Pre-Conditioning and Timing Control for Non-volatile Memory Cells," 7,916,528.

Chen, Y., Li, H., Liu, H., Kim, K., and Huang, H., "Pipeline Sensing Using Voltage Storage Elements to Read Non-volatile Memory Cells," 7,936,625.

Huang, H., Cater, A., Khoury, M., Lu, Y., and Chen, Y., "Table-based Reference Voltage Characterization Scheme," 7,936,629.

Chen, Y., Li, H., Zhu, W., Wang, X., Wang, R., and Liu, H., "Write Method with Voltage Line Tuning," 7,944,730.

Xi, H., Liu, H., Wang, X., Lu, Y., Chen, Y., Zheng, Y., Dimitrov, D.V., Wang, D., and Li, H., "Variable Write and Read Methods for Resistive Random Access Memory," 8,054,675.

Dimitrov, D., Heinonen, O., Chen, Y., Xi, H., and Lou, X., "Electronic Devices Utilizing Spin Torque Transfer To Flip Magnetic Orientation," 8,077,503.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Computer Memory Device with Status Register," 8.081,504.

Chen, Y., Reed, D., Lu, Y., Liu, H., and Li, H., "Computer Memory Device with Multiple Interfaces," 8,194,437.

Li, H., Chen, Y., Liu, H., Huang, H., and Wang, R., "Write Current Compensation Using Word Line Boosting Circuitry," 8,203,893.

Dimitrov, D., Heinonen, O., Chen, Y., Xi, H., and Lou, X., "Magnetic Random Access Memory (MRAM) Devices Utilizing Magnetic Flip-flop Structures," 8,295,072.

Chen, Y., Li, H., Liu, H., Lu, Y., and Xue, S., "Data Devices Including Multiple Error Correction Codes and Methods of Utilizing," 8,296,620.

Chen, Y., Li, H., Liu, H., Xi, H., and Xue, S., "Memory Hierarchy Containing Only Non-volatile Cache," US Patent Pending, 20100057984.

Li, H., Chen, Y., Liu, H., and Huang, H., "Non-volatile Resistive Sense Memory On-chip Cache," US Patent Pending, 20100095957.

Li, H., Chen, Y., Liu, H., Setiadi, D., and Lee, B., "Pipelined Memory Access Method and Architecture therefore," US Patent Pending, 20100037020.

Li, H., Chen, Y., Wang, X., Xi, H., Zhu, W., and Roelofs, A., "Quiescent Testing of Non-volatile Memory Array," US Patent Pending, 201000238700.

Huang, H., and Chen, Y., "Non-volatile Associative Memory with Hybrid Index Tag Array," US Patent Pending, 20100228912.

Lu, Y., Liu, H., Khoury, M., and Chen, Y., "Bipolar CMOS Select Device for Resistive Sense Memory," US Patent Pending, 20100177554.

Wang, X., Zhu, W., Huang, H., Chen, Y., and Xi, H., "Tunable Random Bit Generator with Magnetic Tunnel Junction," US Patent Pending, 20100109660.

Liu, H., Wang, X., Lu, Y., and Chen, Y., "High Density Reconfigurable Spin Torque Non-volatile Memory Device," US Patent Pending, 20100091546.